PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 535
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F46K80-I/P
Manufacturer Part Number
PIC18F46K80-I/P
Description
40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F46K80-I/P
A/d Inputs
11-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
1K Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PDIP
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F46K80-I/PT
Manufacturer:
BROADCOM
Quantity:
101
Company:
Part Number:
PIC18F46K80-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F46K80-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2011 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
OFST
FSR2
Contents
of 0A2Ch
W
Contents
of 0A2Ch
Q1
ADD W to Indexed
(Indexed Literal Offset mode)
ADDWF
0 k 95
d [0,1]
(W) + ((FSR2) + k) dest
N, OV, C, DC, Z
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘ 0 ’, the result is stored in W. If ‘d’
is ‘ 1 ’, the result is stored back in
register ‘f’ (default).
1
1
Read ‘k’
ADDWF
0010
Q2
=
=
=
=
=
=
[OFST] ,0
[k] {,d}
01d0
17h
2Ch
0A00h
20h
37h
20h
Process
Data
Q3
kkkk
destination
Write to
Q4
kkkk
Preliminary
PIC18F66K80 FAMILY
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
Decode
FLAG_OFST
FSR2
Contents
of 0A0Ah
Contents
of 0A0Ah
OFST
FSR2
Contents
of 0A2Ch
Contents
of 0A2Ch
Q1
Q1
register ‘f’
BSF
Bit Set Indexed
(Indexed Literal Offset mode)
BSF [k], b
0 f 95
0 b 7
1 ((FSR2) + k)<b>
None
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
1
1
Set Indexed
(Indexed Literal Offset mode)
SETF [k]
0 k 95
FFh ((FSR2) + k)
None
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
1
1
Read ‘k’
SETF
Read
1000
0110
Q2
Q2
=
=
=
=
=
=
=
=
2Ch
0A00h
00h
FFh
[FLAG_OFST], 7
[OFST]
bbb0
1000
0Ah
0A00h
55h
D5h
Process
Process
Data
Data
Q3
Q3
DS39977C-page 535
kkkk
kkkk
destination
Write to
register
Write
Q4
Q4
kkkk
kkkk
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