71M6541D-IGT/F Maxim Integrated Products, 71M6541D-IGT/F Datasheet - Page 55
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71M6541D-IGT/F
Manufacturer Part Number
71M6541D-IGT/F
Description
PMIC Solutions Precision Energy Meter IC
Manufacturer
Maxim Integrated Products
Type
Metering SoCr
Datasheet
1.71M6541F-DB.pdf
(165 pages)
Specifications of 71M6541D-IGT/F
Core
8051
Core Architecture
8051
Data Bus Width
8 bit
Data Ram Size
3 KB
Device Million Instructions Per Second
5 MIPS
Interface Type
I2C, ICE, SPI, UART
Maximum Clock Frequency
5 MHz
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Programmable I/os
30
Number Of Timers
2
On-chip Adc
22 bit
Operating Supply Voltage
3 V to 3.6 V
Package / Case
LQFP-64
Processor Series
8051
Program Memory Size
32 KB
Program Memory Type
Flash
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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4. Set the LKP_WR bit (I/O RAM 0x2889[0]) to write the 8-bit datum into NV_RAM
The NV RAM table can also be read by writing a 1 into the LKP_RD bit (I/O RAM 0x2889[1]). The process of
For proper operation, the MPU must load the lookup table with values that reflect the crystal properties
with respect to temperature, which is typically done once during initialization. Since the lookup table is
not directly addressable, the MPU uses the following procedure to load the entire NV RAM table:
1. Set the LKPAUTOI bit (I/O RAM 0x2887[7]) to enable address auto-increment.
2. Write zero into the I/O RAM register LKPADDR[6:0] (I/O RAM 0x2887[6:0]).
3. Write the 8-bit datum into I/O RAM register LKPDAT (I/O RAM 0x2888).
5.
6. Repeat steps 3 through 5 until all data has been written to NV RAM.
reading from and writing to the NV RAM is accelerated by setting the LKPAUTOI bit (I/O RAM 0x2887[7]).
When LKPAUTOI is set, LKPADDR[6:0] auto-incremented every time LKP_RD or LKP_WR is pulsed. It is
also possible to perform random access of the NV RAM by writing a 0 to the LKPAUTOI bit and loading the
desired address into LKPADDR[6:0].
2.5.4.5 RTC Interrupts
The RTC generates interrupts each second and each minute. These interrupts are called RTC_1SEC and
RTC_1MIN. In addition, the RTC functions as an alarm clock by generating an interrupt when the minutes
and hours registers both equal their respective target counts as defined in Table 45. The alarm clock
interrupt is called RTC_T. All three interrupts appear in the MPU’s external interrupt 6. See
in the interrupt section for the enable bits and flags for these interrupts.
The target registers for minutes and hours are listed in
v1.1
Name
RTC_TMIN[5:0]
RTC_THR[4:0]
Wait for LKP_WR to clear (LKP_WR auto-clears when the data has been copied to NV RAM).
If the oscillator temperature compensation feature is not being used, it is possible to use the NV
RAM storage area as ordinary NV storage space using the procedure described above to read and
write NV RAM data. In this case, keep the OSC_COMP bit (I/O RAM 0x28A0[5]) reset to disable the
automatic oscillator temperature compensation feature.
Location Rst
289E[5:0]
289F[4:0]
252
253
254
255
…
0
1
2
3
4
5
6
7
© 2008–2011 Teridian Semiconductor Corporation
Table 45: I/O RAM Registers for RTC Interrupts
0
0
104.40
104.73
105.06
105.39
22.00
22.33
22.65
22.98
23.31
23.64
23.96
24.29
…
Wk
0
0
R/W The target minutes register. See RTC_THR[4:0] below.
R/W The target hours register. The RTC_T interrupt occurs
Dir
Description
when RTC_MIN becomes equal to RTC_TMIN and
RTC_HR becomes equal to RTC_THR.
63
…
0
1
Table
45.
63
…
0
1
105.06
22.65
23.96
…
Table 33
55
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