71M6541D-IGT/F Maxim Integrated Products, 71M6541D-IGT/F Datasheet - Page 65

• Manufacturer Part Number: 71M6541D-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6541D-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 3 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 30
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-64
• Processor Series: 8051
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.5.8.4 LCD Drivers
The LCD drivers are grouped into up to six commons (COM0 – COM5) and up to 56 segment drivers.
The LCD interface is flexible and can drive 7-segment digits, 14-segments digits or enunciator symbols.
A voltage doubler and a contrast DAC generate VLCD from either VBAT or V3P3SYS, depending on the
V3P3SYS voltage. The voltage doubler, while capable of driving into a 500 kΩ load, is able to generate a
maximum LCD voltage that is within 1 V of twice the supply voltage. The doubler and DAC operate from
a trimmed low-power reference.
The configuration of the VLCD generation is controlled by the I/O RAM field LCD_VMODE[1:0] (I/O RAM
0x2401[7:6]). It is decoded into the LCD_EXT, LDAC_E, and LCD_BSTE internal signals.
details the LCD_VMODE[1:0] configurations.
The voltage doubler is active in all LCD modes including the LCD mode when LCD_BSTE = 1. Current
dissipation in LCD mode can be reduced if the boost circuit is disabled and the LCD system is operated
directly from VBAT.
The LCD DAC uses a low-power reference and, within the constraints of VBAT and the voltage doubler,
generates a VLCD voltage of 2.5 VDC + 2.5 * LCD_DAC[4:0]/31.
The LCD_BAT bit (I/O RAM 0x2402[7]) causes the LCD system to use the battery voltage in all power
modes. This may be useful when an external supply is available for the LCD system. The advantage of
connecting the external supply to VBAT, rather than VLCD is that the LCD DAC is still active.
If LCD_EXT = 1, the VLCD pin must be driven from an external source. In this case, the LCD DAC has
no effect.
v1.1
LCD_VMODE [1:0]
Notes:
1. LCD_EXT, LDAC_E and LCD_BSTE are 71M654x internal signals which are decoded from
2. V3P3L is an internal supply rail that is supplied from either the VBAT pin or the V3P3SYS
11
10
01
00
When using the VLCD boost circuit, use care when setting the LCD_DAC[4:0] (I/O RAM 0x240D[4:0])
value to ensure that the LCD manufacturer’s recommended operating voltage specification is not
exceeded.
the LCD_VMODE[1:0] control field setting (I/O RAM 0x2401[7:6]). Each of these decoded
signals, when asserted, has the effect indicated in the description column above, and as
summarized below.
pin, depending on the V3P3SYS pin voltage. When the V3P3SYS pin drops below 3.0 VDC,
the 71M654x switches to BRN mode and V3P3L is sourced from the VBAT pin, otherwise
V3P3L is sourced from the V3P3SYS pin while in MSN mode.
LCD_EXT : When set, the VLCD pin expects an external supply voltage
LDAC_E : When set, LCD DAC is enabled
LCD_BSTE : When set, the LCD boost circuit is enabled
LCD_EXT LDAC_E LCD_BSTE Description
1
0
0
0
© 2008–2011 Teridian Semiconductor Corporation
Table 56: LCD_VMODE[1:0] Configurations
0
1
1
0
0
1
0
0
External VLCD connected to the VLCD pin.
See note 2 below for the definition of V3P3L.
LCD boost is enabled. The maximum VLCD pin
voltage is 2*V3P3L-1.
In general, the VLCD pin voltage is as follows:
VLCD = max(2*V3P3L-1, 2.5(1+LCD_DAC[4:0]/31)
LCD boost is disabled. The maximum VLCD
voltage is V3P3L.
VLCD = max(V3P3L, 2.5V+2.5*LCD_DAC[4:0]/31)
VLCD=V3P3L, LCD DAC and LCD boost are
disabled. In LCD mode, this setting causes the
lowest battery current.
Table 56
65