71M6541D-IGT/F Maxim Integrated Products, 71M6541D-IGT/F Datasheet - Page 60

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71M6541D-IGT/F

Manufacturer Part Number
71M6541D-IGT/F
Description
PMIC Solutions Precision Energy Meter IC
Manufacturer
Maxim Integrated Products
Type
Metering SoCr
Datasheet

Specifications of 71M6541D-IGT/F

Core
8051
Core Architecture
8051
Data Bus Width
8 bit
Data Ram Size
3 KB
Device Million Instructions Per Second
5 MIPS
Interface Type
I2C, ICE, SPI, UART
Maximum Clock Frequency
5 MHz
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Programmable I/os
30
Number Of Timers
2
On-chip Adc
22 bit
Operating Supply Voltage
3 V to 3.6 V
Package / Case
LQFP-64
Processor Series
8051
Program Memory Size
32 KB
Program Memory Type
Flash
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
60
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as
shown in
to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT. See
6.4.6 V3P3D Switch
Sourcing current in or out of DIO pins other than those dedicated for wake functions, for
example with pull-up or pull-down resistors, must be avoided. Violating this rule leads to
increased quiescent current in sleep and LCD modes.
Note:
Resources are selectable only on SEGDIO2 through SEGDIO11 and the
PB pin. See
Value in DIO_Rn[2:0]
Figure 20,
Not recommended
HIGH-Z
Figure 20: Connecting an External Load to DIO Pins
HIGH
LOW
5
Table 48
© 2008–2011 Teridian Semiconductor Corporation
BROWNOUT
MISSION
LCD/SLEEP
right), not source it from V3P3D (as shown in
on page 143.
(71M6541D/F) and
DIO
V3P3SYS
V3P3D
GNDD
VBAT
Resource Selected for SEGDIOn or PB Pin
Low priority I/O interrupt (INT1)
Table 52
Recommended
HIGH-Z
HIGH
LOW
BROWNOUT
MISSION
LCD/SLEEP
(71M6542F).
DIO
V3P3SYS
VBAT
V3P3D
GNDD
Figure
20, left). This is due
v1.1

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