71M6541D-IGT/F Maxim Integrated Products, 71M6541D-IGT/F Datasheet - Page 75

• Manufacturer Part Number: 71M6541D-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6541D-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 3 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 30
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-64
• Processor Series: 8051
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

v1.1
Command Sequence
ADDR 1xxx xxxx STATUS
Byte0 ... ByteN
0xxx xxxx ADDR Byte0 ...
ByteN
(From Host) SPI_CSZ
(From Host) SPI_CSZ
(From 654x) SPI_DO
(From 654x) SPI_DO
(From Host) SPI_CK
(From Host) SPI_CK
SERIAL READ
SERIAL WRITE
(From Host) SPI_DI
(From Host) SPI_DI
x
Figure 27: SPI Slave Port - Typical Multi-Byte Read and Write operations
A15
A15
0
0
A14
A14
16 bit Address
16 bit Address
A1
A1
© 2008–2011 Teridian Semiconductor Corporation
HI Z
HI Z
15
15
A0
A0
Description
Read data starting at ADDR. ADDR auto-increments until SPI_CSZ is
raised. Upon completion, SPI_CMD (SFR 0xFD) is updated to 1xxx xxxx
and an SPI interrupt is generated. The exception is if the command byte
is 1000 0000. In this case, no MPU interrupt is generated and SPI_CMD
is not updated.
Write data starting at ADDR. ADDR auto-increments until SPI_CSZ is
raised. Upon completion, SPI_CMD is updated to 0xxx xxxx and an SPI
interrupt is generated. The exception is if the command byte is 0000
0000. In this case, no MPU interrupt is generated and SPI_CMD is not
updated.
Table 63: SPI Command Sequences
16
16
C7
C7
C6
C6
8 bit CMD
8 bit CMD
C5
C5
23
23
C0
C0
ST7
ST7
24
24
ST6
ST6
Status Byte
Status Byte
ST5
ST5
ST0
ST0
31
31
32
32
D7
D7
x
D6
D6
DATA[ADDR]
DATA[ADDR]
D1
D1
D0
D0
39
39
D7
D7
40
40
Extended Read . . .
Extended Write . . .
DATA[ADDR+1]
D6
DATA[ADDR+1]
D6
D1
D1
47
D0
47
D0
x
75