PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 179

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

CIR1
CIX1
Note: Access is always granted by default to the ISAC-SX with TIC-Bus Address
4.1.20
Value after reset: FE
CODR1 ... C/I-Code 1 Receive
CICW, CI1E ... C/I-Channel Width, C/I-Channel 1 Interrupt Enable
These two bits contain the read back values from CIX1 register (see below).
4.1.21
Value after reset: FE
CODX1 ... C/I-Code 1 Transmit
Bits 7-2 of C/I-channel 1.
CICW... C/I-Channel Width
CICW selects between a 4 bit (’0’) and 6 bit (’1’) C/I1 channel width.
The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher
two bits are ignored for interrupt generation. However in write direction the full CODX1
code is transmitted, i.e. the host must write the higher two bits to “1”.
CI1E ... C/I-Channel 1 Interrupt Enable
Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled (1) or masked (0).
Data Sheet
(TBA2-0, STCR register) ’7’, which has the lowest priority in a bus configuration.
7
7
CIR1 - Command/Indication Receive 1
CIX1 - Command/Indication Transmit 1
H
H
CODR1
CODX1
179
Detailed Register Description
CICW CI1E
CICW CI1E
0
0
PEB 3086
2003-01-30
ISAC-SX
WR (2F)
RD (2F)