PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 50

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.3.2
According to ITU recommendation I.430 a multiframe provides extra layer 1 capacity in
the TE-to-NT direction by using an extra channel between the TE and NT (Q-channel).
The Q bits are defined to be the bits in the F
In the NT-to-TE direction the S-channel bits are used for information transmission. One
S channel (S1) out of five possible S-channels can be accessed by the ISAC-SX.
In the NT-to-TE direction the S-channel bits are used for information transmission.
The S and Q channels are accessed via the µC interface or the IOM-2 MONITOR
channel, respectively, by reading/writing the SQR or SQX bits in the S/Q channel
registers (SQRRx, SQXRx).
Table 8
Table 8
Frame Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
Data Sheet
shows the S and Q bit positions within the multiframe.
S/T-Interface Multiframing
S/Q-Bit Position Identification and Multiframe Structure
NT-to-TE
F
ONE
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
A
Bit Position
NT-to-TE
M Bit
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
50
A
bit position.
Description of Functional Blocks
NT-to-TE
S Bit
S11
S21
S31
S41
S51
S12
S22
S32
S42
S52
S13
S23
S33
S43
S53
S14
S24
S34
S44
S54
S11
S21
TE-to-NT
F
Q1
ZERO
ZERO
ZERO
ZERO
Q2
ZERO
ZERO
ZERO
ZERO
Q3
ZERO
ZERO
ZERO
ZERO
Q4
ZERO
ZERO
ZERO
ZERO
Q1
ZERO
A
Bit Position
PEB 3086
2003-01-30
ISAC-SX