PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 77

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.5.1.3
Command
Activation Request with
priority class 8
Activation Request with
priority class 10
Activation Request Loop ARL
Deactivation Indication
Reset
Timing
Test mode SSP
Test mode SCP
Note: In the activated states (AI8, AI10 or AIL indication) the 2B+D channels are only
Indication
Deactivation Request
Reset
Test Mode
Acknowledge
Slip Detected
Resynchronization
during level detect
Data Sheet
transferred transparently to the S/T interface if one of the three “Activation
Request” commands is permanently issued.
C/I Codes (TE, LT-T)
Abbr. Code Remark
DR
RES
TMA
SLD
RSY
Abbr. Code Remark
AR8
AR10 1001 Activation requested by the ISAC-SX, D-
DI
RES
TIM
SSP
SCP
0000 Deactivation request via S/T-interface if left
0001 Reset acknowledge
0010 Acknowledge for both SSP and SCP
0011
0100 Signal received, receiver not synchronous
1000 Activation requested by the ISAC-SX, D-
1010 Activation requested for the internal or
1111 Deactivation Indication
0001 Reset of the layer-1 statemachine
0000 Layer-2 device requires clocks to be
0010 One AMI-coded pulse transmitted in each
0011 AMI-coded pulses transmitted continuously,
from F7/F8
channel priority set to 8 (see note)
channel priority set to 10 (see note)
external Loop A (see note).
For a non transparent internal loop bit
DIS_TX of register TR_CONF2 has to be set
to ’1’ additionally.
activated
frame, resulting in a frequency of the
fundamental mode of 2 kHz
resulting in a frequency of the fundamental
mode of 96 kHz
77
Description of Functional Blocks
PEB 3086
2003-01-30
ISAC-SX