PEF24911HV22XP Lantiq, PEF24911HV22XP Datasheet - Page 28
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PEF24911HV22XP
Manufacturer Part Number
PEF24911HV22XP
Description
Manufacturer
Lantiq
Datasheet
1.PEF24911HV22XP.pdf
(155 pages)
Specifications of PEF24911HV22XP
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Table 1
Pin No.
61
JTAG Boundary Scan
64
1
2
3
63
Power Supply Pins
6, 22, 38, 54
9, 25, 41, 57
Data Sheet
OD:
PuP:
PD:
PU:
Open Drain
Push Pull
Internal Pull Down (e.g.. 10 to 20 kOhms)
Internal Pull Up (e.g.. 10 to 20 kOhms)
Pin Definitions and Functions (cont’d)
Symbol
CLS3
TCK
TMS
TDI
TDO
TRST
VDD
VSS
Input (I)
Output (O)
O
I
I
(PU)
I
(PU)
O
I
(PU)
Function
12 msec clock synchronized to the received
Superframe of Port 3
can be used for monitoring and test purposes
Note: The delay between both signals may
Test Clock
Test Mode Select
internal pullup resistor (160 k )
Test Data Input
internal pullup resistor (160 k )
Test Data Output
JTAG Boundary Scan Disable
resets the TAP controller state machine
(asynchronous reset), active low, internal
pullup (160 k ). Clamp TRST to GND if the
Boundary Scan logic is not used
’1’= reset inactive
’0’= reset active
3.3V 0.3V supply voltage
0V ground
18
vary from activation to activation.
Pin Descriptions
PEF 24911
2001-07-16
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