ZL2106ALCF Intersil, ZL2106ALCF Datasheet - Page 13

• Manufacturer Part Number: ZL2106ALCF
• Description: 6A Digital DC-DC Converter W/ DDC - BULK50
• Manufacturer: Intersil
• Series: -r
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of ZL2106ALCF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.54 V ~ 5.5 V
• Current - Output: 6A
• Frequency - Switching: 200kHz ~ 1MHz
• Voltage - Input: 4.5 V ~ 14 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STEP #
1
2
3
4
5
TABLE 4. RESISTORS FOR SETTING OUTPUT VOLTAGE
Internal Memory Check The device will check for values stored in its internal memory. This step is also
Multi-mode Pin Check
Pre-ramp Delay
Power Applied
Device Ready
STEP NAME
R
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
28.7
31.6
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
82.5
90.9
(kΩ)
100
121
133
147
162
178
110
10
11
75
SET
13
Input voltage is applied to the ZL2106’s VDD pins (VDDP and VDDS).
performed after a Restore command.
The device loads values configured by the multi-mode pins.
The device is ready to accept an enable signal.
The device requires approximately 2ms following an enable signal and prior to
ramping its output. Additional pre-ramp delay may be configured using the SS pin.
0.75
1.25
V
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
5.0
(V)
OUT
TABLE 3. ZL2106 START-UP SEQUENCE
ZL2106
DESCRIPTION
The resistor setting method can be used to set the output voltage to
levels not available in Table 2. To set V
4 to select the resistor that corresponds to the desired voltage.
The output voltage may also be set to any value between 0.6V
and 5.0V using the I
for details.
Start-up Procedure
The ZL2106 follows a specific internal start-up procedure after
power is applied to the VDD pins (VDDP and VDDS). Table 3
describes the start-up sequence.
If the device is to be synchronized to an external clock source, the
clock frequency must be stable prior to asserting the EN pin. The
device requires approximately 5ms to 10ms to check for specific
values stored in its internal memory. If the user has stored values
in memory, those values will be loaded. The device will then
check the status of all multi-mode pins and load the values
associated with the pin settings.
Once this process is completed, the device is ready to accept
commands via the I
to be enabled. Once enabled, the device requires approximately
2ms before its output voltage may be allowed to start its
ramp-up process. If a soft-start delay period less than 2ms has
been configured (using PMBus commands), the device will
default to a 2ms delay period. If a delay period greater than 2ms
is configured, the device will wait for the configured delay period
prior to starting to ramp its output.
After the delay period has expired, the output will begin to ramp
towards its target voltage according to the pre-configured soft-
start ramp time that has been set using the SS pin. It should be
noted that if the EN pin is tied to VDDP or VDDS, the device will
still require approximately 5ms to 10ms before the output can
begin its ramp-up as described in Table 3.
Soft-start Delay and Ramp Times
It may be necessary to set a delay from when an enable signal is
received until the output voltage starts to ramp to its target
value. In addition, the designer may wish to set the time required
for V
expired. These features may be used as part of an overall inrush
current management strategy or to control how fast a load IC is
turned on. The ZL2106 gives the system designer several options
for precisely and independently controlling both the delay and
ramp time periods.
OUT
to ramp to its target value after the delay period has
2
2
C/SMBus interface and the device is ready
C interface. See Application Note AN2033
ignore an enable signal or PMBus
Approx 5ms to 10ms (device will
Depends on input supply ramp
OUT
traffic during this period)
Approximately 2ms
using resistors, use Table
TIME DURATION
time
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FN6852.4