ZL2106ALCF Intersil, ZL2106ALCF Datasheet - Page 18

• Manufacturer Part Number: ZL2106ALCF
• Description: 6A Digital DC-DC Converter W/ DDC - BULK50
• Manufacturer: Intersil
• Series: -r
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of ZL2106ALCF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.54 V ~ 5.5 V
• Current - Output: 6A
• Frequency - Switching: 200kHz ~ 1MHz
• Voltage - Input: 4.5 V ~ 14 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10X the value of C
voltage on it to droop excessively during a C
C
This capacitor is used to both stabilize and provide noise filtering
for the analog 5V reference supply. It should be between 2.2µF
and 10µF, should use a semi-stable X5R or X7R dielectric
ceramic capacitor with a low ESR (less than 10mΩ) and should
have a rating of 6.3V or more.
THERMAL CONSIDERATIONS
In typical applications, the ZL2106’s high efficiency will limit the
internal power dissipation inside the package. However, in
applications that require a high ambient operating temperature
the user must perform some thermal analysis to ensure that the
ZL2106’s maximum junction temperature is not exceeded.
The ZL2106 has a maximum junction temperature limit of
+125°C, and the internal over-temperature limiting circuitry will
force the device to shut down if its junction temperature exceeds
this threshold. In order to calculate the maximum junction
temperature, the user must first calculate the power dissipated
inside the IC (P
The maximum operating junction temperature can then be
calculated using Equation 12:
Where T
temperature and θ
for the ZL2106 package.
Current Sensing and Current Limit Threshold
Selection
The ZL2106 incorporates a patented “lossless” current sensing
method across the internal low-side MOSFET that is independent
of r
the gain, which does not represent a r
of the internal current sensing circuit can be modified by the
IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands.
The design should include a current limiting mechanism to
protect the power supply from damage and prevent excessive
current from being drawn from the input supply in the event that
the output is shorted to ground or an overload condition is
imposed on the output. Current limiting is accomplished by
sensing the current through the circuit during a portion of the
duty cycle. The current limit threshold is set to 9A by default. The
current limit threshold can set to a custom value via the
I
for further details.
Additionally, the ZL2106 gives the power supply designer several
choices for the fault response during over or under current
conditions. The user can select the number of violations allowed
before declaring a fault, a blanking time and the action taken when
a fault is detected. The blanking time represents the time when no
current measurement is taken. This is to avoid taking a reading just
after a current load step (less accurate due to potential ringing).
Please refer to Application note AN2033 for further details.
T
P
2
VRA
Q
C/SMBus interface. Please refer to Application Note AN2033
j
max
DS(ON)
=
(
SELECTION
I
=
LOAD
PCB
T
variations, including temperature. The default value for
PCB
is the expected maximum printed circuit board
2
)
[
Q
(
+
R
) as expressed in Equation 11:
DS
(
B
JC
P
so that a discharged C
(
Q
ON
is the junction-to-case thermal resistance
×
)
QH
θ
JC
)
( )
D
)
18
+
(
R
DS
DS(ON)
(
ON
)
B
QL
B
value, and the offset
does not cause the
)
recharge pulse.
(
1
−
D
)
]
(EQ. 11)
(EQ. 12)
ZL2106
Loop Compensation
The ZL2106 operates as a voltage-mode synchronous buck
controller with a fixed frequency PWM scheme. Although the
ZL2106 uses a digital control loop, it operates much like a
traditional analog PWM controller. Figure 17 is a simplified block
diagram of the ZL2106 control loop, which differs from an analog
control loop only by the constants in the PWM and compensation
blocks. As in the analog controller case, the compensation block
compares the output voltage to the desired voltage reference and
compensation zeroes are added to keep the loop stable. The
resulting integrated error signal is used to drive the PWM logic,
converting the error signal to a duty cycle to drive the internal
MOSFETs.
TABLE 12. RESISTOR SETTING FOR LOOP COMPENSATION
G
24
27
27
27
27
27
27
27
27
27
27
30
30
30
30
30
30
30
30
30
30
33
(dB)
FIGURE 17. CONTROL LOOP BLOCK DIAGRAM
DPWM
0.150
0.150
0.150
0.150
0.300
0.300
0.300
0.300
0.600
0.600
0.600
0.150
0.150
0.150
0.300
0.300
0.300
0.300
0.600
0.600
0.600
0.150
Q
1-D
D
Compensation
115.000
115.000
115.000
115.000
115.000
115.000
69.147
41.577
69.147
41.577
25.000
69.147
41.577
25.000
69.147
41.577
69.147
41.577
25.000
69.147
41.577
25.000
V
fsw/fn
IN
L
R
C
C
R
O
High or 12.1
Open or 11
Low or 10
13.3
14.7
19.6
21.5
23.7
26.1
28.7
31.6
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
75.0
16.2
17.8
(k)
FC
V
OUT
FN6852.4