NAND01GR3B2CZA6E Micron Technology Inc, NAND01GR3B2CZA6E Datasheet - Page 43

• Manufacturer Part Number: NAND01GR3B2CZA6E
• Manufacturer: Micron Technology Inc

Specifications of NAND01GR3B2CZA6E

• Cell Type: NAND
• Density: 1Gb
• Access Time (max): 25us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Program/erase Volt (typ): 1.7 to 1.95V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.95V
• Word Size: 8b
• Number Of Words: 128M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / Rohs Status: Compliant

NAND01G-B2C
8.3
8.4
8.5
8.6
8.6.1
8.6.2
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page, and
the previous page is marked as invalid. After several updates it is necessary to remove
invalid pages to free some memory space.
To free this memory space and allow further program operations it is recommended to
implement a garbage collection algorithm. In a garbage collection software the valid pages
are copied into a free area and the block containing the invalid pages is erased (see
Figure
Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear-leveling algorithm
to monitor and spread the number of write cycles per block.
In memories that do not use a wear-leveling algorithm not all blocks get used at the same
rate. Blocks with long-lived data do not endure as many write cycles as the blocks with
frequently-changed data.
The wear-leveling algorithm ensures that equal use is made of all the available write cycles
for each block. There are two wear-leveling levels:
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
Error correction code
Users must implement an error correction code (ECC) to identify and correct errors in data
stored in NAND flash memories. The ECC implemented must be able to correct 1 bit every
512 bytes. Sensible data stored in spare area must be covered by ECC as well.
Hardware simulation models
Behavioral simulation models
Denali Software Corporation models are platform independent functional models designed
to assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic behavior and timings of NAND flash devices, and so allow
software to be developed before hardware.
IBIS simulation models
IBIS (I/O buffer information specification) models describe the behavior of the I/O buffers
and electrical characteristics of flash devices.
First level wear-leveling, new data is programmed to the free blocks that have had the
fewest write cycles
Second level wear-leveling, long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.
19).
Software algorithms
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