MT41J64M16JT-15E:G Micron Technology Inc, MT41J64M16JT-15E:G Datasheet - Page 101

• Manufacturer Part Number: MT41J64M16JT-15E:G
• Description: MICMT41J64M16JT-15E:G DDR3 SDRAM 64MB X1
• Manufacturer: Micron Technology Inc
• Series: -r
• Type: DDR3 SDRAMr

Specifications of MT41J64M16JT-15E:G

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 96-TFBGA
• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 355mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Write Leveling
Figure 48: Write Leveling Concept
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
Destination
Source
Destination
Differential DQS
Differential DQS
Differential DQS
CK#
CK#
CK#
DQ
DQ
CK
CK
CK
Tn
Tn
T0
Push DQS to capture
For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for
the commands, addresses, control signals, and clocks. Write leveling is a scheme for the
memory controller to adjust or deskew the DQS strobe (DQS, DQS#) to CK relationship
at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is
generally used as part of the initialization process, if required. For normal DRAM opera-
tion, this feature must be disabled. This is the only DRAM operation where the DQS
functions as an input (to capture the incoming clock) and the DQ function as outputs (to
report the state of the clock). Note that nonstandard ODT schemes are required.
The memory controller using the write leveling procedure must have adjustable delay
settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins.
This is accomplished when the DRAM asynchronously feeds back the CK status via the
DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the
DQS strobe until a CK transition from “0” to “1” is detected. The DQS delay established
through this procedure helps ensure
that use fly-by topology by deskewing the trace length mismatch. A conceptual timing of
this procedure is shown in Figure 48.
0–1 transition
T0
T0
T1
T1
T1
T2
0
101
T2
T2
1
T3
t
DQSS,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
t
T4
DSS, and
1Gb: x4, x8, x16 DDR3 SDRAM
0
T4
T4
t
DSH specifications in systems
1
T5
©2006 Micron Technology, Inc. All rights reserved.
T5
T5
T6
Commands
Don’t Care
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T6
T7