MT41J64M16JT-15E:G Micron Technology Inc, MT41J64M16JT-15E:G Datasheet - Page 141

• Manufacturer Part Number: MT41J64M16JT-15E:G
• Description: MICMT41J64M16JT-15E:G DDR3 SDRAM 64MB X1
• Manufacturer: Micron Technology Inc
• Series: -r
• Type: DDR3 SDRAMr

Specifications of MT41J64M16JT-15E:G

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 96-TFBGA
• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 355mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 86: Write Burst
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
Command 1
DQS, DQS#
DQS, DQS#
DQS, DQS#
Address 2
DQ 3
DQ 3
DQ 3
CK#
CK
t DQSS (NOM)
t DQSS (MAX)
t DQSS (MIN)
WRITE
Bank,
Col n
T0
Notes:
NOP
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the
3. DI n = data-in for column n.
4. BL8, WL = 5 (AL = 0, CWL = 5).
5.
6.
WL = AL + CWL
times.
WRITE command at T0.
t
t
ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
NOP
T2
DQSS must be met at each rising clock edge.
WPST is usually depicted as ending at the crossing of DQS, DQS#; however,
NOP
T3
t DQSH
NOP
T4
t DQSH
t WPRE
t WPRE
t DQSH
t DQSL
141
t DQSL
t WPRE
t DQSS t DSH
t DSS
DI
n
t DSS
t DQSH
t DQSL
NOP
DI
T5
n
t DQSS
t DQSH
t DSH
n + 1
DI
DI
n
t DQSH
t DQSL
n + 1
DI
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DQSL
n + 2
t DSS
n + 1
DI
DI
t DSS
t DQSH
t DQSL
NOP
n + 2
T6
DI
t DSH
t DQSH
t DSH
n + 3
n + 2
DI
DI
t DQSH
t DQSL
n + 3
DI
1Gb: x4, x8, x16 DDR3 SDRAM
t DQSL
n + 4
t DSS
n + 3
DI
DI
t DSS
t DQSH
t DQSL
n + 4
NOP
T7
DI
t DSH
t DQSH
t DSH
n + 4
n + 5
DI
DI
t DQSH
t DQSL
n + 5
DI
t DQSL
n + 6
t DSS
n + 5
DI
DI
t DSS
t DQSH
t DQSL
n + 6
NOP
T8
DI
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t DSH
t DQSH
t DSH
n + 7
n + 6
DI
DI
t DQSH
t WPST
t DQSL
n + 7
Transitioning Data
DI
t DQSL
t WPST
t DSS
n + 7
DI
t DSS
t WPST
t DQSL
NOP
T9
t
Operations
WPST actually
Don’t Care
T10
NOP