DS2181AQ/T&R Maxim Integrated Products, DS2181AQ/T&R Datasheet
DS2181AQ/T&R
Specifications of DS2181AQ/T&R
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DS2181AQ/T&R Summary of contents
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FEATURES Single chip primary rate transceiver meets CCITT standards G.704, G.706 and G.732 Supports new CRC4-based framing standards and CAS and CCS signaling standards Simple serial interface used for device configuration and control in processor mode Hardware mode requires ...
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DESCRIPTION The DS2181A is designed for use in CEPT networks and supports all logical requirements of CCITT Red Book Recommendations G.704, G.706 and G.732. The transmit side generates framing patterns and CRC4 codes, formats outgoing channel and signaling data, and ...
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TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1 PIN SYMBOL TYPE 1 TMSYNC I 2 TFSYNC I 3 TCLK I 4 TCHCLK O 5 TSER I 6 TMO O 7 TXD I 8 TSTS O 9 TSD I 10 TIND ...
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NOTES: 1. These output status pins are only available on the DS2181AQ the TEST pin is tied low and CCR.1=0, then these pins will be tri–stated. RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY) Table 2B PIN SYMBOL TYPE 21 ...
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PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 3 PIN SYMBOL TYPE 14 O INT 15 SDI I 16 SDO SCLK I 19 SPS I POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 4 PIN ...
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REGISTER SUMMARY Table 5 REGISTE ADDRE T RIMR 0000 R RSR 0001 R BVCR 0010 R CECR 0011 R FECR 0100 R RCR 0101 R CCR 0110 T/R TCR 0111 T TIR1 1000 T TIR2 1001 TIR3 1010 ...
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ADDRESS/COMMAND An address/command byte write must precede any read or write of the port registers. The first bit written (LSB) of the address/command byte specifies read or write. The following nibble identifies register address. The next 2 bits are reserved ...
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SERIAL PORT READ/WRITE Figure 3 NOTES: 1. SDI sampled on rising edge of SCLK. 2. SDO updated on falling edge of SCLK. TCR: TRANSMIT CONTROL REGISTER Figure 4 (MSB) TUA1 TSS TSM SYMBOL POSITION TUA1 TCR.7 TSS TCR.6 TSM TCR.5 ...
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NOTE: 1. When the common channel signaling mode is enabled (TCR.5 = 1), the TSD input is disabled internally; all timeslot 16 data is sampled at TSER. CCR: COMMON CONTROL REGISTER Figure 5 (MSB) - TAFP THDE SYMBOL POSITION - ...
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RCR: RECEIVE CONTROL REGISTER Figure 6 (MSB RSM SYMBOL POSITION - RCR.7 - RCR.6 RSM RCR.5 CMSC RCR.4 CMRC RCR.3 FRC RCR.2 SYNCE RCR.1 RESYNC RCR.0 CEPT FRAME STRUCTURE The CEPT frame is made 8-bit ...
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CCS SIGNALLING CCS (selected when TCR and/or when RCR utilizes all bit positions of timeslot 16 in every frame for message-oriented signaling data transmission. In CCS mode one can use either timeslot 16 or any one ...
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FIXED FRAME RESYNC CRITERIA When enabled via RCR.1, the device will automatically initiate frame search whenever the frame alignment word is received in error three consecutive times. FIXED CAS MULTIFRAME RESYNC CRITERIA When enabled via RCR.1, the device will automatically ...
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TSD INPUT TIMING Figure 7 CAS OUTPUT FORMAT IN TIMESLOT 16 Figure 8 1 FRAME 0 0000XYXX ABCD for Timeslot 1 NOTE: 1. Timeslot 16 of frame 0 is reserved for the multiframe alignment word (0000), distant multiframe alarm (Y) ...
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Bits 4 through 8 of timeslot 0 in non-align frames are reserved for national use. When TCR the transmitted national bits are sourced from register locations TINR.4 through TINR.0. If TCR the national bits are sampled ...
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TRANSMIT TIMING A low-high transition at TMSYNC once per multiframe (every 2 milliseconds multiple of the multiframe rate establishes outgoing CAS and/or CRC4 multiframe alignment. Output TMO indicates that alignment. A low-high transition at TFSYNC at the ...
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TRANSMIT MULTIFRAME BOUNDARY TIMING Figure 13 NOTES: 1. Low-high transitions on TMSYNC and/or TFSYNC must occur one TCLK period early with respect to actual frame and multiframe boundaries. TMO follows the rising edge of TMSYNC or TFSYNC. 2. TAF transitions ...
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RECEIVE SIGNALING Table 7 1 FRAME # RSD VALID DURING TIMESLOT # 0 15 ...
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NOTE: 1. The CAS multiframe can start with an align or non-align frame. The CRC4 multiframe always starts with an align frame. RSD TIMING Figure DS2181A ...
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RECEIVE MULTIFRAME BOUNDARY TIMING Figure 17 NOTES: 1. Low-high transitions on RMSYNC and RFSYNC occur one RCLK period early with respect to actual frame and multiframe boundaries. 2. RAF transitions on true frame boundaries. 3. Delay from RPOS, RNEG to ...
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RSR: RECEIVE STATUS REGISTER Figure 18 (MSB) RRA RDMA RSA1 SYMBOL POSITION RRA RSR.7 RDMA RSR.6 RSA1 RSR.5 RUA1 RSR.4 FSERR RSR.3 MFSERR RSR.2 RLOS RSR.1 ECS RSR.0 NOTE: 1. When in the CCS mode, the RDMA flag bit and ...
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RIMR: RECEIVE INTERRUPT MASK REGISTER Figure 19 (MSB) RRA RDMA RSA1 SYMBOL POSITION RRA RIMR.7 RDMA RIMR.6 RSA1 RIMR.5 RUA1 RIMR.4 FSERR RIMR.3 MFSERR RIMR.2 RLOS RIMR.1 ECS RIMR.0 ALARM REPORTING AND INTERRUPT SERVICING Alarm and error conditions are reported ...
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CECR: CRC4 ERROR COUNT REGISTER Figure 21 (MSB) CRC7 CRC6 CRC5 SYMBOL POSITION CRC7 BVCR.7 CRC0 BVCR.0 FECR: FRAME ERROR COUNT REGISTER Figure 22 (MSB) FE7 FE6 FE5 SYMBOL POSITION FE7 FECR.7 FE0 FECR.0 ERROR LOGGING The BVCR, CECR and ...
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RDMA RDMA transitions high when bit 6 of timeslot 16 in frame 0 is set for three consecutive occasions and returns low when the bit is clear for three consecutive occasions. The RDMA bit (RSR. latched version of ...
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CRC4 SUB-MULTIFRAME 2 ERRORED Figure 25 FRAME ALIGNMENT WORD ERRORED Figure 26 CRC4 SUB-MULTIFRAME 1 ERRORED Figure 27 NOTES FOR FIGURES 23 THROUGH 27: 1. CAS multiframe alignment word received in error; RFER will transition high at first error occurrence ...
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RESET A high-low transition on RST initiated until returns high. RST the hardware mode. Following reset, the host processor should update all on-chip registers to establish desired operating modes. HARDWARE MODE An on-chip hardware control mode simplifies preliminary system prototyping ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the ...
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SERIAL PORT WRITE AC TIMING DIAGRAM Figure 28 NOTE: 1. Shaded regions indicate “don’t care” states of input data. 1 SERIAL PORT READ AC TIMING Figure 29 NOTE: 1. Serial port write must precede a port read to provide address ...
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AC ELECTRICAL CHARACTERISTICS PARAMETER SDI to SCLK Setup SCLK to SDI Hold SCLK Low Time SCLK High Time SCLK Rise and Fall Time to SCLK Setup CS SCLK to Hold CS Inactive Time CS SLK to SDO Valid to SDO ...
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AC ELECTRICAL CHARACTERISTICS PARAMETER Propagation Delay RCLK to RMSYNC, RFSYNC, RSTS, RCHCLK, RAF Propagation Delay RCLK to RSER, RSD Transition Time All Outputs RCLK Period RCLK Pulse Width RCLK Rise and Fall Times RPOS, RNEG Setup to RCLK Falling RPOS, ...
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TRANSMIT AC TIMING DIAGRAM Figure 30 RECEIVE AC TIMING DIAGRAM Figure DS2181A ...
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DS2181A CEPT TRANSCEIVER (600-MIL DIP) 40-PIN DIM INCHES MIN MAX 2.050 2.075 0.530 0.550 0.140 0.160 0.600 0.625 0.015 0.040 0.120 0.145 0.090 0.110 0.625 0.675 0.008 0.012 0.015 ...
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DS2181AQ CEPT TRANSCEIVER (PLCC) DIM CH1 INCHES MIN MAX 0.165 0.180 0.090 0.120 0.020 - 0.026 0.033 0.013 0.021 0.009 0.012 0.042 0.048 0.685 0.695 0.650 ...