DS2181AQ/T&R Maxim Integrated Products, DS2181AQ/T&R Datasheet - Page 6

• Manufacturer Part Number: DS2181AQ/T&R
• Description: IC TXRX CEPT PRIMARY RATE 44PLCC
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS2181AQ/T&R

• Number Of Drivers/receivers: 1/1
• Protocol: CEPT
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC, 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

REGISTER SUMMARY Table 5
NOTES:
1. Transmit or receive side register.
2. RSR is a read only register; all other registers are read/write.
3. Reserved bit locations must be programmed to 0.
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2181A serve as a microprocessor/ microcontroller-compatible serial port.
Fourteen on-chip registers allow the user to update operational characteristics and monitor device status
via a host controller, minimizing hardware interfaces.
Port read/write timing is unrelated to the chip transmit and receive timing, allowing asynchronous reads
and/ or writes by the host. The timing set is identical to that of 8051-type microcontrollers operating in
serial port mode 0. For proper operation of the port and the transmit and receive registers, the user should
provide TCLK and RCLK as well as SCLK.
REGISTE
BVCR
RIMR
CECR
FECR
TINR
TIR1
TIR2
TIR3
TIR4
RCR
CCR
TCR
TXR
RSR
R
ADDRE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
SS
T/R
T/R
R
R
R
R
R
R
T
T
T
T
2
1
Receive Interrupt Mask Register. Allows masking of alarm
generated interrupts.
Receive Status Register. Reports all receive alarm conditions.
Bipolar Violation Count Register. 8-bit presettable counter
which records individual bipolar violations.
CRC4 Error Count Register. 8-bit presettable counter which
records individual errors.
Frame Error Count Register. 8-bit presettable counter which
logs individual errors in the received frame alignment signal.
Receive Control Register. Establishes receive side operating
characteristics.
Common Control Register. Establishes additional operating
characteristics for transmit and receive sides.
Transmit Control Register. Establishes transmit side operation
characteristics.
Transmit Idle Registers. Designates which outgoing timeslots are
to be substituted with idle code.
Transmit International and National Register. When enabled via
the TCR, contents inserted into the outgoing national and/or
international bit positions.
Transmit Extra Register. When enabled via the TCR, contents
inserted into the out going extra bit positions.
6 of 32
DESCRIPTION/FUNCTION
DS2181A