DS2181AQ/T&R Maxim Integrated Products, DS2181AQ/T&R Datasheet - Page 25

• Manufacturer Part Number: DS2181AQ/T&R
• Description: IC TXRX CEPT PRIMARY RATE 44PLCC
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS2181AQ/T&R

• Number Of Drivers/receivers: 1/1
• Protocol: CEPT
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC, 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RESET
A high-low transition on
initiated until
the hardware mode. Following reset, the host processor should update all on-chip registers to establish
desired operating modes.
HARDWARE MODE
An on-chip hardware control mode simplifies preliminary system prototyping and serves applications
which do not require the features of the serial port. Tying SPS low disables the serial port, clears all
internal register locations except those shown below, and redefines pins 14 through 18 as mode control
inputs. The mode control inputs establish device operational characteristics as shown in Table 8. The
hardware mode simplifies device retrofit into existing applications where control interfaces are designed
with discrete logic.
HARDWARE MODE CONTROL Table 8
NOTE:
1. Pin numbers for PLCC package are listed in parenthesis.
PIN NUMBER
(16)
(17)
(18)
(19)
(20)
14
15
16
17
18
RST
returns high.
RST
REGISTER LOCATION
clears all internal registers except the three error counters; a resync is
RST
CCR.5/CCR.4
CCR.3/CCR.2
TCR.5/RCR.5
TINR.5
must be held low on system power-up and when switching to/from
TXR.2
25 of 32
TRA - Transmit Remote Alarm
0 = Normal operation
1 = Enable alarm
TDMA - Transmit Distant Multiframe
Alarm
0 = Normal operation
1 = Enable alarm
Data Format
0 = Input and output data AMI coded
1 = Input and output data HDB3 coded
Transmit and Receive CRC4 Multiframe
0 = Disabled
1 = Enabled
Transmit and Receive CAS Multiframe
0 = Enabled
1 = Disabled
NAME AND DESCRIPTION
DS2181A