DS2181AQ/T&R Maxim Integrated Products, DS2181AQ/T&R Datasheet - Page 8

IC TXRX CEPT PRIMARY RATE 44PLCC

DS2181AQ/T&R

Manufacturer Part Number
DS2181AQ/T&R
Description
IC TXRX CEPT PRIMARY RATE 44PLCC
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet

Specifications of DS2181AQ/T&R

Number Of Drivers/receivers
1/1
Protocol
CEPT
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
44-LCC, 44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS2181AQ/T&RDS2181AQ/T&R
Manufacturer:
Maxim Integrated
Quantity:
10 000
SERIAL PORT READ/WRITE Figure 3
NOTES:
1. SDI sampled on rising edge of SCLK.
2. SDO updated on falling edge of SCLK.
TCR: TRANSMIT CONTROL REGISTER Figure 4
(MSB)
SYMBOL
TUA1
TUA1
TSA1
ODM
INBS
TSM
NBS
XBS
TSS
TSS
POSITION
TCR.7
TCR.6
TCR.5
TCR.4
TCR.3
TCR.2
TCR.1
TCR.0
TSM
NAME AND DESCRIPTION
Transmit Unframed All 1’s.
0 = Normal operation.
1 = Replace outgoing data at TPOS and TNEG with unframed all
1’s code.
Transmit Signaling Select
0 = Signaling data embedded in the serial bit stream is sampled at
TSER during timeslot 16.
1 = Signaling data is channel associated and sampled at TSD as
shown in Table 6.
Transmit Signaling Mode
0 = Channel Associated Signaling (CAS).
1 = Common Channel Signaling (CCS).
International Bit Select
0 = Sample international bit at TIND.
1 = Outgoing international bit = TINR.7.
National Bit Select
0 = Sample national bits at TIND.
1 = Source outgoing national bits from TINR.4 through TINR.0.
Extra Bit Select
0 = Sample extra bits at TXD.
1 = Source extra bits from TXR.0 through TXR.1 and TXR.3.
Transmit Signaling All 1’s
0 = Normal operation.
1 = Force contents of timeslot 16 in all frames to all 1’s.
Output Data Mode
0 = TPOS and TNEG outputs are 100% duty cycle.
1 = TPOS and TNEG outputs are 50% duty cycle.
INBS
8 of 32
NBS
1
1
XBS
TSA1
(LSB)
ODM
DS2181A

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