DS2181AQ/T&R Maxim Integrated Products, DS2181AQ/T&R Datasheet - Page 16

• Manufacturer Part Number: DS2181AQ/T&R
• Description: IC TXRX CEPT PRIMARY RATE 44PLCC
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS2181AQ/T&R

• Number Of Drivers/receivers: 1/1
• Protocol: CEPT
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC, 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS2181A
TRANSMIT MULTIFRAME BOUNDARY TIMING Figure 13
NOTES:
1. Low-high transitions on TMSYNC and/or TFSYNC must occur one TCLK period early with respect
to actual frame and multiframe boundaries. TMO follows the rising edge of TMSYNC or TFSYNC.
2. TAF transitions on true frame boundaries.
3. Delay from TSER to TPOS, TNEG is five TCLK periods.
TRANSMIT SIGNALING TIMESLOT TIMING Figure 14
RECEIVE SIGNALING
Receive signaling data is available at two outputs: RSER and RSD. RSER outputs the signaling data in
timeslot 16 at RSER. The signaling data is also extracted from timeslot 16 and presented at RSD during
the timeslots shown in Table 7. This channel-associated signaling simplifies CAS system design.
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