CS8952-CQ Cirrus Logic Inc, CS8952-CQ Datasheet - Page 30

• Manufacturer Part Number: CS8952-CQ
• Description: IC ETHNT 10/100 TXRX 5V 100-TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-CQ

• Mounting Type: Surface Mount
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 100-TQFP, 100-VQFP
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• Transceiver Type: Ethernet
• Leaded Process Compatible: No
• No. Of Drivers: 6
• Interface Type: MII
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1205

A read transaction is indicated by an Opcode of 10
and a write by 01.
The PHY Address is five bits, with the most signif-
icant bit sent first. If the PHY address included in
the frame is not 00000 or does not match the PHY-
AD field of the Self Status Register (address 19h),
the rest of the frame is ignored.
The register address is five bits, with the most sig-
nificant bit sent first, and indicates the CS8952 reg-
ister to be written to/read from.
The Turnaround time is a two bit time spacing be-
tween when the MAC drives the last register ad-
dress bit onto MDIO and the data field of a
management frame in order to avoid contention
during a read transaction. For a read transaction,
the MAC should tri-state the MDIO pin beginning
on the first bit time, and the CS8952 will begin
driving the MDIO signal to a logic ZERO during
the second bit time. During write transactions,
since the MDIO direction does not need to be re-
versed, the MAC will drive the MDIO to a logic
ONE for the first bit time and a logic ZERO for the
second.
The data field is always 16 bits in length, with the
most significant bit sent first.
5. CONFIGURATION
The CS8952 can be configured in a variety of ways.
All control and status information can be accessed
via the MII Serial Management Interface. Addi-
tionally, many configuration options can be set at
power-up or reset times via individual control lines.
Some configuration capabilities are available at
any time via individual control lines.
5.1
At power-up and reset time, the following pins are
30
Configuration At Power-up/Reset
Time
Register Address
0h
1h
Basic Mode Control Register
Basic Mode Status Register
Description
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
5.2
The following pins are for dedicated control signals
and can be used at any time to configure the
CS8952.
5.3
The CS8952 supports configuration by software
control through the use of 16-bit configuration and
status registers accessed via the MDIO/MDC pins
(MII Management Interface). The first seven regis-
ters are defined by the IEEE 802.3 specification.
Additional registers extend the register set to pro-
vide enhanced monitoring and control capabilities.
6. CS8952 REGISTERS
The CS8952 register set is comprised of the 16-bit
status and control registers described below. A de-
tailed description each register follows.
10BT_SER
AN[1:0]
BP4B5B
BPALIGN
BPSCR
ISODEF
LPSTRT
PHYAD[4:0]
REPEATER
MII_DRV
TCM
TXSLEW[1:0] Set 100BASE-TX transmitter output
Pin Name
Pin Name
PWRDN
RESET
LPBK
Configuration Via Control Pins
Configuration via the MII
Select 10BASE-T serial mode
Select auto-negotiation mode
Bypass 4B5B coders
Bypass 4B5B coders and scramblers
Bypass scramblers, enter FX mode
Electrically isolate MII after reset
Start in low power mode
Set MII PHY address
Control definition of CRS pin, enable
carrier integrity monitor and SQE func-
tion
Set MII driver strength
Set TX_CLK mode
slew rate
Enter loopback mode
Enter power-down mode
Reset
Function
Function
Read/Write
Read-Only
Type
CS8952