CS8952-CQ Cirrus Logic Inc, CS8952-CQ Datasheet - Page 35

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CS8952-CQ

Manufacturer Part Number
CS8952-CQ
Description
IC ETHNT 10/100 TXRX 5V 100-TQFP
Manufacturer
Cirrus Logic Inc
Type
Transceiverr
Datasheet

Specifications of CS8952-CQ

Mounting Type
Surface Mount
Protocol
MII
Voltage - Supply
4.75 V ~ 5.25 V
Package / Case
100-TQFP, 100-VQFP
Peak Reflow Compatible (260 C)
No
Supply Voltage
5V
Supply Voltage Max
5V
Transceiver Type
Ethernet
Leaded Process Compatible
No
No. Of Drivers
6
Interface Type
MII
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
Other names
598-1205

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CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
3
2
1
0
BIT
Auto-Neg Ability
Link Status
Jabber Detect
Extended Capability Read Only 1
NAME
Read Only 1
Read Only 0
Read Only 0
TYPE
RESET
This bit indicates that the CS8952 has auto-negotia-
tion capability. Therefore this bit will always read
back a value of 1.
When set, this bit indicates that a valid link has been
established. Upon a link failure, this bit is cleared and
latched. It will remain cleared until this register is
read.
In 10BASE-T mode, if the last transmission is longer
than 105 ms, then the packet output is terminated by
the jabber logic and this bit is set. If JabberiE (Inter-
rupt Mask Register (address 10h), bit 3) is set, an MII
Interrupt will be generated.
This bit is implemented with a latching function so
that the occurrence of a jabber condition causes it to
become set until it is cleared by a read to this regis-
ter, a read to the Interrupt Status Register (address
11h), or a reset.
No jabber detect function has been defined for
100BASE-TX.
This bit indicates that an extended register set may
be accessed (registers beyond address 01h). This bit
always reads back a value of 1.
DESCRIPTION
CS8952
35

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