CS8952-CQ Cirrus Logic Inc, CS8952-CQ Datasheet - Page 45

• Manufacturer Part Number: CS8952-CQ
• Description: IC ETHNT 10/100 TXRX 5V 100-TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-CQ

• Mounting Type: Surface Mount
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 100-TQFP, 100-VQFP
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• Transceiver Type: Ethernet
• Leaded Process Compatible: No
• No. Of Drivers: 6
• Interface Type: MII
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1205

6.10
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
15
14
13
12
11
10
9
BIT
Complete
CIM Link
Unstable
Reset
15
7
CIM Link Unstable
Link Status Change Read Only 0
Descrambler Lock
Change
Premature End
Error
DCR Rollover
FCCR Rollover
RECR Rollover
Interrupt Status Register - Address 11h
NAME
This register indicates which event(s) caused an interrupt event on the MII_IRQ pin. All bits are self-
clearing, and will thus be cleared upon readout.
Link Status
Change
Jabber
Detect
14
6
Read Only 0
Read Only 0
Read Only 0
Read Only 0
Read Only 0
Read Only 0
Lock Change
Descrambler
Auto-Neg
Complete
TYPE
13
5
Premature End
Detection Fault
Parallel
RESET
Error
12
4
Rollover
Parallel
When set, this bit indicates that an unstable link con-
dition was detected by the Carrier Integrity Monitor
function.
When set, this bit indicates that a change has
occurred to the status of the link. The Self Status
Register (address 19h) may be read to determine the
current status of the link.
When set, this bit indicates that a change has
occurred in the status of the descrambler. The Self
Status Register (address 19h) may be read to deter-
mine the current status of the scrambler lock.
This bit is set when a premature end of frame is
detected for 100 Mb/s operation. A premature end is
defined as two consecutive IDLE patterns detected in
a frame prior to the End of Stream Delimiter.
This bit is set when the MSB of the Disconnect Count
Register (address 12h) becomes set. This should
provide ample warning to the management layer so
that the DCR may be read before rolling over.
This bit is set when the MSB of the False Carrier
Count Register (address 13h) becomes set. This
should provide ample warning to the management
layer so that the FCCR may be read before saturat-
ing.
This bit is set when the MSB of the Receive Error
Count Register (address 15h) becomes set. This
should provide ample warning to the management
layer so that the RECR may be read before rolling
over.
DCR
Fail
11
3
Rollover
Remote
FCCR
Fault
10
2
DESCRIPTION
Received
Rollover
RECR
Page
9
1
CS8952
Loopback
Reserved
Remote
Fault
8
0
45