Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 191

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
ESPI Baud Rate High and Low Byte Registers
Table 95. ESPISTATE Values and Description (Continued)
The ESPI Baud Rate High and Low Byte registers (see Tables 96 and 97) combine to form
a 16-bit reload value, BRG[15:0], for the ESPI Baud Rate Generator. The ESPI baud rate
is calculated using the following equation:
SPI Baud Rate (bps)
Minimum baud rate is obtained by setting BRG[15:0] to
of (2 x 65536 = 131072).
When the ESPI function is disabled, the BRG functions as a basic 16-bit timer with inter-
rupt on timeout.
Follow the procedure below to configure the BRG as a general purpose timer with inter-
rupt on timeout:
1. Disable the ESPI by setting
2. Load the appropriate 16-bit count value into the ESPI Baud Rate High and Low Byte
3. Enable the BRG timer function and associated interrupt by setting the BRGCTL bit in
When configured as a general purpose timer, the SPI BRG interrupt interval is calculated
using the following equation:
SPI BRG Interrupt Interval (s)
ESPISTATE Value
10_0101
10_0010
10_0011
10_0000
10_0001
registers.
the ESPI Control Register to 1.
=
Description
Bit 2 Transmit
Bit 1 Receive
Bit 1 Transmit
Bit 0 Receive
Bit 0 Transmit
System Clock Frequency (Hz)
--------------------------------------------------------------------------- -
P R E L I M I N A R Y
ESPIEN[1:0] = 00
2

BRG[15:0]
=
System Clock Period (s) BRG[15:0]
Z16FMC Series Motor Control MCUs
Enhanced Serial Peripheral Interface
in the SPI Control Register.
0000H
for a clock divisor value
Product Specification

169