Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 56

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Table 8. Stop Mode Recovery Sources and Resulting Action
PS028702-1210
Operating Mode
STOP mode
Stop Mode Recovery Using WDT Timeout
Stop Mode Recovery Using a GPIO Port Pin Transition
Caution:
Mode Recovery, the device is held in Reset for 66 cycles of the internal precision oscilla-
tor.
Stop Mode Recovery only affects the contents of
(see page 35)
does not affect any other values in the register file, including the stack pointer, register
pointer, flags, peripheral control registers and general-purpose RAM.
The Z16FMC CPU fetches the Reset vector at program memory addresses 0004H–0007H
and loads that value into the program counter. Program execution begins at the Reset vec-
tor address. Following Stop Mode Recovery, the STOP bit in
Register (see page 35)
ing actions. The following text provides more detailed information about each of the Stop
Mode Recovery sources.
If the WDT times out during STOP mode, the device undergoes a Stop Mode Recovery
sequence. In
are set to 1. If the WDT is configured to generate a System Exception on timeout, the
ZNeo CPU services the WDT System Exception following the normal Stop Mode Recov-
ery sequence.
Each of the GPIO port pins is configured as a Stop Mode Recovery input source. If any
GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value (from
High to Low or from Low to High) initiates Stop Mode Recovery. The GPIO Stop Mode
Recovery signals are filtered to reject pulses less than 10 ns (typical) in duration. In
Reset Status and Control Register (see page
Short pulses on the port pin initiate Stop Mode Recovery without initiating inter-
rupts (if enabled for the pin).
Stop Mode Recovery Source
WDT timeout when configured for
Reset
WDT timeout when configured for
System Exception
Data transition on any GPIO Port pin
enabled as a Stop Mode Recovery
source
the Reset Status and Control Register (see page
and the
Oscillator Control Register
is set to 1. Table 8 lists the Stop Mode Recovery sources and result-
P R E L I M I N A R Y
35), the STOP bit is set to 1.
Action
Stop Mode Recovery
Stop Mode Recovery followed by WDT
System Exception
Stop Mode Recovery
Z16FMC Series Motor Control MCUs
the Reset Status and Control Register
(see page 289). Stop Mode Recovery
Reset and Stop Mode Recovery
35), the WDT and STOP bits
the Reset Status and Control
Product Specification
the
34