Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 301
![Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC64AG20SG
Manufacturer Part Number
Z16FMC64AG20SG
Description
Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC64AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC64AG20SG
Manufacturer:
Zilog
Quantity:
161
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Table 161. Hardware Breakpoint Register (HWBPn)
PS028702-1210
Bits
6
5
4
3
2
1
0
Bits
Field
RESET
R/W
ADDR
Bits
Field
RESET
R/W
ADDR
Hardware Breakpoint Registers
Description (Continued)
DBGBRK – Debug break
This bit indicates if the CPU has reached a BRK instruction. This bit is set when a BRK instruc-
tion is executed. It is cleared when the DBGHALT control bit is written to zero.
HALT – HALT mode
0 = The device is not in HALT mode.
1 = The device is in HALT mode.
STOP – STOP mode
0 = The device is not in Stop mode.
1 = The device is in Stop mode.
RPEN – Read protect enabled
0 = Memory Read Protect is disabled.
1 = Memory Read Protect is enabled.
Reserved
These bits are reserved and always read back zero.
TDRF – Transmit Data Register full
This bit is set when the transmit data register is full.
0 = Transmit Data Register is empty
1 = Transmit Data Register is full
RDRE – Receive Data Register empty
This bit indicates when the receive data register is empty.
0 = Receive Data Register is full.
1 = Receive Data Register is empty.
R/W R/W R/W R/W
PC
31
15
0
The Hardware Breakpoint Register (HWBPn) is used to set hardware breakpoints.
ST
FF_E090-FF_E091,FF_E094-FF_E095,FF_E098-FF_E099,FF_E09C-FF_E09D
FF_E092-FF_E093,FF_E096-FF_E097,FF_E09A-FF_E09B,FF_E09E-FF_E09F
30
14
0
RD
29
13
0
WR
28
12
0
27
11
26
10
P R E L I M I N A R Y
MASK
0000
R/W
25
9
ADDR[15:0]
24
8
0000H
R/W
23
7
Z16FMC Series Motor Control MCUs
22
6
21
5
ADDR[23:16]
20
4
R/W
00H
Product Specification
19
3
On-Chip Debugger
18
2
17
1
16
0
279
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