MCIMX536AVV8C Freescale Semiconductor, MCIMX536AVV8C Datasheet - Page 15

• Manufacturer Part Number: MCIMX536AVV8C
• Description: IC, 32-BIT MPU, 800 MHz, 529-BGA
• Manufacturer: Freescale Semiconductor
• Series: ARM Cortex-A8r

Specifications of MCIMX536AVV8C

• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 800MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 0.8V To 1.15V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor
Temperature
Mnemonic
Monitor
Block
SRTC
SSI-1
SSI-2
SSI-3
IPTP
TZIC
TVE
Secure Real
Time Clock
I2S/SSI/AC97
Interface
IEEE1588
Precision Time
Protocol
TV Encoder
TrustZone Aware
Interrupt
Controller
(Part of SATA
Block Name
Block)
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Security
Connectivity
Peripherals
Connectivity
Peripherals
System
Control
Peripherals
Multimedia
ARM/Control
Subsystem
The SRTC incorporates a special system state retention register (SSRR)
that stores system parameters during system shutdown modes. This
register and all SRTC counters are powered by dedicated supply rail
NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized
separately even if all other supply rails are shut down. The power for this
block comes from NVCC_SRTC_POW supply. When this supply is driven
by the MC13892 power management controller, this block can be power
backed up through the coin-cell feature of the MC13892. This register is
helpful for storing warm boot parameters. The SSRR also stores the system
security state. In case of a security violation, the SSRR mark the event
(security violation indication).
The SSI is a full-duplex synchronous interface used on the i.MX53A
processor to provide connectivity with off-chip audio peripherals. The SSI
interfaces connect internally to the AUDMUX for mapping to external ports.
The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S,
and AC-97), bit depths (up to 24 bits per word), and clock/frame sync
options.
Each SSI has two pairs of 8 x 24 FIFOs and hardware support for an
external DMA controller in order to minimize its impact on system
performance. The second pair of FIFOs provides hardware interleaving of
a second audio stream, which reduces CPU overhead in use cases where
two time slots are being used simultaneously.
The IEEE 1588-2002 (version 1) standard defines a precision time protocol
(PTP) - which is a time-transfer protocol that enables synchronization of
networks (for example, Ethernet), to a high degree of accuracy and
precision.
The IEEE1588 hardware assist is composed of the two blocks: time stamp
unit and real time clock, which provide the timestamping protocol’s
functionality, generating and reading the needed timestamps.
The hardware-assisted implementation delivers more precise clock
synchronization at significantly lower CPU load compared to purely
software implementations.
The temperature sensor is an internal module to the i.MX53xA that monitors
the die temperature. The monitor is capable in generating SW interrupt, or
trigger the CCM, to reduce the core operating frequency.
The TV encoder, version 2.1 is implemented in conjunction with the image
processing unit (IPU) allowing handheld devices to display captured still
images and video directly on a TV or LCD projector. It supports composite
PAL/NTSC, VGA, S-video, and component up to HD1080p analog video
outputs.
The TrustZone interrupt controller (TZIC) collects interrupt requests from all
i.MX53xA sources and routes them to the ARM core. Each interrupt can be
configured as a normal or a secure interrupt. Software Force Registers and
software Priority Masking are also supported.
Brief Description
Modules List
15