MCIMX536AVV8C Freescale Semiconductor, MCIMX536AVV8C Datasheet - Page 21

• Manufacturer Part Number: MCIMX536AVV8C
• Description: IC, 32-BIT MPU, 800 MHz, 529-BGA
• Manufacturer: Freescale Semiconductor
• Series: ARM Cortex-A8r

Specifications of MCIMX536AVV8C

• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 800MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 0.8V To 1.15V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.1.4
The i.MX53xA device has four external input system clocks, a low frequency (CKIL), a high frequency
(XTAL), and two general purpose CKIH1 and CKIH2 clocks.
The CKIL is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real
time clock operation, and slow system and watch-dog counters. The clock input can be connected to either
external oscillator or a crystal using internal oscillator amplifier.
Freescale Semiconductor
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Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design
must allow for supply tolerances and system voltage drops.
The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than ± 50 mV. Use of supplies with a
tighter tolerance allows reduction of the setpoint with commensurate power savings.
VDDA and VDDAL1 can be driven by the VDD_DIG_PLL internal regulator using external connections. When operating in this
configuration, the regulator is still operating at the default 1.2V, as bootup start. This is acceptable for boot modes when
connecting any or all of these supplies to the internal on-die LDO regulator.
During bootup initialization, software should increase this regulator voltage to match VCC (1.3V nominal) in order to reduce
internal leakage current.
By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In this case, there is no need driving this
supply externally. LDO output to VDD_DIG_PLL should be configured by software after power-up to 1.3 V output. A bypass
capacitor of minimal value 22 μF should be connected to this pad in any case whether it is driven internally or externally. Use
of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.
By default, the VDD_ANA_PLL is driven from internal on-die 1.8 V linear regulator (LDO). In this case there is no need driving
this supply externally. A bypass capacitor of minimal value 22 μF should be connected to this pad in any case whether it is
driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.
In case the VDD_FUSE is kept powered on during Fuse Read mode, the efuse_prog_supply_gate bit in CCM_CGPR register
should be kept low, to avoid the possibility of inadvertently blowing fuses. Alternately, VDD_FUSE can be ground or left
floating, when not in Fuse Write mode.
If not using TVE module or other pads in this power domain for the product, the TVDAC_DHVDD and TVDAC_AHVDDRGB
can remain floating.
GPIO pad operational at low frequency
The analog supplies should be isolated in the application design. Use of series inductors is recommended.
VDD_REG is power supply input for the integrated linear regulators of VDD_ANA_PLL and VDD_DIG_PLL when they are
configured to the internal supply option. VDDR_REG still has to be tied to 2.5 V supply when VDD_ANA_PLL and
VDD_DIG_PLL are configured for external power supply mode although in this case it is not used as supply source.
Lifetime of 43,800 hours based on 105 C junction temperature at nominal supply voltages.
VDD_REG
Symbol
VBUS
VPH
VP
T
External Clock Sources
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i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
See
for details. Note that this is not a power supply.
Power supply input for the integrated linear
regulators
SATA PHY core power supply.
SATA PHY I/O supply voltage
Junction Temperature
Table 4 on page 18
Table 6. i.MX53xA Operating Ranges (continued)
Parameter
and
Table 104 on page 151
Minimum
2.37
1.25
2.25
–40
—
1
Nominal
105
2.5
1.3
2.5
—
Electrical Characteristics
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2
Maximum
2.63
1.35
2.75
125
—
1
Unit
o
—
V
V
V
C
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