MCIMX536AVV8C Freescale Semiconductor, MCIMX536AVV8C Datasheet - Page 62

• Manufacturer Part Number: MCIMX536AVV8C
• Description: IC, 32-BIT MPU, 800 MHz, 529-BGA
• Manufacturer: Freescale Semiconductor
• Series: ARM Cortex-A8r

Specifications of MCIMX536AVV8C

• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 800MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 0.8V To 1.15V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Electrical Characteristics
4.6.7
The DDR2/LVDDR2 interface fully complies with JESD79-2E – DDR2 JEDEC release April, 2008,
supporting DDR2-800 and LVDDR2-800.
The DDR3 interface fully complies with JESD79-3D – DDR3 JEDEC release April 2008 supporting
DDR3-800.
The LPDDR2 interface fully complies with JESD209-2B, supporting LPDDR2-800.
62
1
2
3
4
5
6
7
MAXD
WE47
WE48
Parameters WE4... WE21 value see column BCD = 0 in
All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units.
CS Assertion. This bit field determines when CS signal is asserted during read/write cycles.
CS Negation. This bit field determines when CS signal is negated during read/write cycles.
t is axi_clk cycle time.
BE Assertion. This bit field determines when BE signal is asserted during read cycles.
BE Negation. This bit field determines when BE signal is negated during read cycles.
Ref
No.
TI
Table 39. EIM Asynchronous Timing Parameters Table (continued)Relative Chip Select
DTACK MAXIMUM delay from
Dtack Active to CSx_B Invalid
chip dtack input to its internal
DDR SDRAM Specific Parameters (DDR2/LVDDR2, LPDDR2 and
DDR3)
CSx_B Invalid to Dtack
FF + 2 cycles for
synchronization
Parameter
invalid
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Synchronous measured
MAXCO - MAXCSO +
Determination by
parameters
Table 38
MAXDTI
0
12
MAXCSO +
MAXCO -
MAXDTI
Min
—
0
supported by
(If 133 Mhz is
Freescale Semiconductor
SOC)
Max
—
—
—
Unit
—
ns
ns