MCIMX536AVV8C Freescale Semiconductor, MCIMX536AVV8C Datasheet - Page 161

• Manufacturer Part Number: MCIMX536AVV8C
• Description: IC, 32-BIT MPU, 800 MHz, 529-BGA
• Manufacturer: Freescale Semiconductor
• Series: ARM Cortex-A8r

Specifications of MCIMX536AVV8C

• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 800MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 0.8V To 1.15V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor
DISP0_DAT9
DRAM_A0
DRAM_A1
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A14
DRAM_A15
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_CALIB
RATION
DRAM_CAS
DRAM_CS0
DRAM_CS1
Package Pin
Name
E2
M19
L21
K19
L22
L20
L23
N18
M18
M20
N20
K20
N21
M22
N22
N23
M21
M23
L18
K18
P19
Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Assign
ment
Pin
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
NVCC_LCD
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
Power Rail
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
special
DDR3
DDR3
DDR3
GPIO
DDR3
DDR3
DDR3
DDR3
DDR3
I/O Buffer
Type
Mode
ALT1
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
—
ALT0
ALT0
ALT0
Alt.
GPIO-4 gpio4_GPIO[30]
EXTMC emi_DRAM_A[0]
EXTMC emi_DRAM_A[1]
EXTMC emi_DRAM_A[10
EXTMC emi_DRAM_A[11
EXTMC emi_DRAM_A[12
EXTMC emi_DRAM_A[13
EXTMC emi_DRAM_A[14
EXTMC emi_DRAM_A[15
EXTMC emi_DRAM_A[2]
EXTMC emi_DRAM_A[3]
EXTMC emi_DRAM_A[4]
EXTMC emi_DRAM_A[5]
EXTMC emi_DRAM_A[6]
EXTMC emi_DRAM_A[7]
EXTMC emi_DRAM_A[8]
EXTMC emi_DRAM_A[9]
—
EXTMC emi_DRAM_CAS
EXTMC emi_DRAM_CS[
EXTMC emi_DRAM_CS[
Package Information and Contact Assignments
Out of Reset Condition
]
]
]
]
]
]
(used in DRAM
driver calibration.
See Special
Signal
Considerations
{add xref} above)
0]
1]
Block I/O
Directio
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
n
1
100 KΩ PU
Config./
Value
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
—
161