ADV7180BSTZ Analog Devices Inc, ADV7180BSTZ Datasheet - Page 18

• Manufacturer Part Number: ADV7180BSTZ
• Description: IC VIDEO DECODER SDTV 64-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7180BSTZ

• Design Resources: Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
• Applications: Digital Cameras, Mobile Phones, Portable Video
• Voltage - Supply, Analog: 1.71 V ~ 1.89 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Resolution (bits): 10bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 57.27MSPS
• Power Dissipation Pd: 15µW
• No. Of Input Channels: 6
• Supply Voltage Range: 1.71V To 1.89V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7180LQEBZ - BOARD EVALUATION ADV7180EVAL-ADV7180LFEBZ - BOARD EVAL FOR ADV7180 LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADV7180
INPUT CONFIGURATION
The following are the two key steps for configuring the
ADV7180 to correctly decode the input video:
1.
2.
INSEL[3:0], Input Selection, Address 0x00[3:0]
The INSEL bits allow the user to select the input format. They
also configure the standard definition processor core to process
composite (CVBS), S-Video (Y/C), or component (YPrPb) format.
INSEL[3:0] has predefined analog input routing schemes that
do not require manual mux programming (see Table 13 and
Table 14). This allows the user to route the various video signal
types to the decoder and select them using INSEL[3:0] only.
The added benefit is that if, for example, the CVBS input is
selected, the remaining channels are powered down.
VIDEO FORMAT. USE PREDEFINED
LQFP-64
LQFP-48
REFER TO
TABLE 13
SET INSEL[3:0] TO CONFIGURE
CONNECT ANALOG VIDEO
Use INSEL[3:0] to configure the routing and format decoding
(CVBS, Y/C, or YPrPb). For the 64-lead and 48-lead LQFP,
see Table 13. For the 40-lead and 32-lead LFCSP, see Table 14.
If the input requirements are not met using the INSEL[3:0]
options, the analog input muxing section must be configured
manually to correctly route the video from the analog
input pins to the ADC. The standard definition processor
block, which decodes the digital data, should be configured
to process the CVBS, Y/C, or YPrPb format. This is performed
by INSEL[3:0] selection.
SIGNALS TO ADV7180.
FORMAT/ROUTING.
YES
Figure 14. Signal Routing Options
REFER TO
TABLE 14
LFCSP-40
LFCSP-32
NO
MUX_0[2:0], MUX_1[2:0], MUX_2[2:0].
MANUAL MUXING CONTROL BITS:
CONFIGURE ADC INPUTS USING
SEE TABLE 15.
Rev. F | Page 18 of 116
Table 13. 64-Lead and 48-Lead LQFP INSEL[3:0]
INSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011 to 1111
Table 14. 40-Lead and 32-Lead LFCSP INSEL[3:0]
INSEL[3:0]
0000
0001 to 0010
0011
0100
0101
0110
0111 to 1000
1001
1010 to 1111
Composite
Composite
Composite
Composite
Composite
Composite
Y/C (S-Video)
Y/C (S-Video)
Y/C (S-Video)
YPrPb
YPrPb
Composite
Composite
Composite
R
Y/C (S-Video)
YPrPb
Video Format
Reserved
Video Format
Reserved
Reserved
Reserved
Y input on A
C input on A
Y input on A
C input on A
Y input on A
C input on A
Y input on A
Pb input on A
Pr input on A
Y input on A
Pr input on A
Pb input on A
Not used
Y input on A
C input on A
Y input on A
Pr input on A
Pb input on A
Analog Input
CVBS input on A
CVBS input on A
CVBS input on A
CVBS input on A
CVBS input on A
CVBS input on A
Reserved
Analog Input
CVBS input on A
Reserved
CVBS input on A
CVBS input on A
Reserved
Reserved
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
1
4
2
5
3
6
1
IN
2
IN
1
2
1
IN
5
6
3
4
3
2
IN
IN
IN
IN
IN
IN
IN
IN
IN
1
2
3
4
5
6
1
2
3