ADV7180BSTZ Analog Devices Inc, ADV7180BSTZ Datasheet - Page 98

• Manufacturer Part Number: ADV7180BSTZ
• Description: IC VIDEO DECODER SDTV 64-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7180BSTZ

• Design Resources: Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
• Applications: Digital Cameras, Mobile Phones, Portable Video
• Voltage - Supply, Analog: 1.71 V ~ 1.89 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Resolution (bits): 10bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 57.27MSPS
• Power Dissipation Pd: 15µW
• No. Of Input Channels: 6
• Supply Voltage Range: 1.71V To 1.89V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7180LQEBZ - BOARD EVALUATION ADV7180EVAL-ADV7180LFEBZ - BOARD EVAL FOR ADV7180 LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADV7180
Table 108. Register Map Descriptions (Interrupt Operation)
Address Register
0x40
0x42
0x43
0x44
Interrupt Configuration 1
Interrupt Status 1
(read only)
Interrupt Clear 1
(write only)
Interrupt Mask 1
(read/write)
User Sub Map
Bit Description
INTRQ_OP_SEL[1:0]; interrupt
drive level select
MPU_STIM_INTRQ; manual
interrupt set mode
Reserved
MV_INTRQ_SEL[1:0];
Macrovision interrupt select
INTRQ_DUR_SEL[1:0];
interrupt duration select
SD_LOCK_Q
SD_UNLOCK_Q
Reserved
SD_FR_CHNG_Q
MV_PS_CS_Q
Reserved
SD_LOCK_CLR
SD_UNLOCK_CLR
Reserved
SD_FR_CHNG_CLR
MV_PS_CS_CLR
Reserved
SD_LOCK_MSK
SD_UNLOCK_MSK
Reserved
SD_FR_CHNG_MSK
MV_PS_CS_MSK
Reserved
Rev. F | Page 98 of 116
7 6 5 4 3 2 1 0
0 0
0 1
1 0
1 1
x
x
x
1, 2
Bit
0
1
0
1
0
1
(Shading Indicates
Default State)
0 0
0 1
1 0
1 1
0
1
0
1
0
1
x x x
0 0 0
0 0 0
x
0
1
0 0
0 1
1 0
1 1
0
1
0
1
0
1
0
1
0
1
0
1
Comments
Manual interrupt mode disabled
Not used
Clears MV_PS_CS_Q bit
Masks SD_LOCK_Q bit
Not used
Open drain
Drive low when active
Drive high when active
Reserved
Manual interrupt mode enabled
Not used
Reserved
Pseudo sync only
Color stripe only
Pseudo sync or color stripe
Three XTAL periods
15 XTAL periods
63 XTAL periods
Active until cleared
No change
SD input has caused the decoder to go
from an unlocked state to a locked state
No change
SD input has caused the decoder to go
from a locked state to an unlocked state
No change
Denotes a change in the free-run status
No change
Pseudo sync/color striping detected;
see Register 0x40 MV_INTRQ_SEL[1:0]
for selection
Do not clear
Clears SD_LOCK_Q bit
Do not clear
Clears SD_UNLOCK_Q bit
Do not clear
Clears SD_FR_CHNG_Q bit
Do not clear
Not used
Unmasks SD_LOCK_Q bit
Masks SD_UNLOCK_Q bit
Unmasks SD_UNLOCK_Q bit
Masks SD_FR_CHNG_Q bit
Unmasks SD_FR_CHNG_Q bit
Masks MV_PS_CS_Q bit
Unmasks MV_PS_CS_Q bit
Not used
Notes
These bits can be cleared
or masked in Register 0x43
and Register 0x44, res-
pectively