PCA9502BS,151 NXP Semiconductors, PCA9502BS,151 Datasheet
PCA9502BS,151
Specifications of PCA9502BS,151
935281363151
PCA9502BS-S
Related parts for PCA9502BS,151
PCA9502BS,151 Summary of contents
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PCA9502 8-bit I/O expander with I Rev. 03 — 13 October 2006 1. General description The PCA9502 is an 8-bit I/O expander with very small HVQFN24 package, which makes it ideally suitable for hand-held, battery operated applications. ...
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... NXP Semiconductors 4. Ordering information Table 1. Type number PCA9502BS 5. Block diagram Fig 1. Block diagram of PCA9502 I Fig 2. Block diagram of PCA9502 SPI interface PCA9502_3 Product data sheet Ordering information Package Name Description HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning terminal 1 index area RESET a. I Fig 3. Pin configuration for HVQFN24 6.2 Pin description Table 2. Symbol RESET V DD I2C/SPI CS/A0 SI/A1 SO SCL/SCLK SDA PCA9502_3 Product data sheet 1 18 GPIO4 GPIO3 DD PCA9502BS GPIO2 GPIO1 GPIO0 002aab839 ...
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... NXP Semiconductors Table 2. Symbol IRQ GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 [1] See 7. Functional description The device interfaces to a host through either I I2C/SPI pin), and provides the host with eight programmable GPIO pins. 7.1 Hardware reset, Power-On Reset (POR) and software reset ...
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... NXP Semiconductors 7.2 Interrupts The PCA9502 has interrupt generation capability. The interrupt enable register (IOIntEna) enables interrupts due to I/O pin change of state, and the IRQ signal in response to an interrupt generation. 8. Register descriptions The programming combinations for register selection are shown in Table 5. ...
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... NXP Semiconductors 8.2 Programmable I/O pins State register (IOState) When ‘read’, this register returns the actual state of all I/O pins. When ‘write’, each register bit will be transferred to the corresponding IO pin programmed as output. Table 8. Bit 7:0 8.3 I/O Interrupt Enable register (IOIntEna) This register enables the interrupt due to a change in the I/O confi ...
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... NXP Semiconductors C-bus operation The two lines of the I lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the bus is not busy. Each device is recognized by a unique address whether microcomputer, LCD driver, memory or keyboard interface and can operate as either a transmitter or receiver, depending on the function of the device ...
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... NXP Semiconductors SDA MSB SCL START condition 2 Fig 6. Data transfer on the I C-bus data output by transmitter data output by receiver SCL from master S START condition 2 Fig 7. Acknowledge on the I C-bus A slave receiver must generate an acknowledge after the reception of each byte, and a master must generate one after the reception of each byte clocked out of the slave transmitter. There is an exception to the ‘ ...
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... NXP Semiconductors SDA SCL START address condition Fig 8. A complete data transfer When an address is sent, each device in the system compares the first seven bits after the START with its own address. If there is a match, the device will consider itself addressed by the master, and will send an acknowledge. The device could also determine if in this transaction it is assigned the role of a slave receiver or slave transmitter, depending on the R/W bit ...
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... NXP Semiconductors master write: S SLAVE ADDRESS START condition master read: S SLAVE ADDRESS START condition combined S SLAVE ADDRESS formats: START condition read or 2 Fig 9. I C-bus data formats PCA9502_3 Product data sheet data transferred (n bytes + acknowledge DATA A write acknowledge acknowledge data transferred ...
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... NXP Semiconductors 9.3 Addressing Before any data is transmitted or received, the master must send the address of the receiver via the SDA line. The first byte after the START condition carries the address of the slave device and the read/write bit. be selected by using A1 and A0 pins. For example, if these 2 pins are connected to V then the PCA9502’ ...
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... NXP Semiconductors S SLAVE ADDRESS White block: host to PCA9502 Grey block: PCA9502 to host Fig 10. Master writes to slave The register read cycle (see sending a slave address with the direction bit set to ‘write’ with a following sub-address. Then, in order to reverse the direction of the transfer, the master issues a repeated START followed again by the device address, but this time with the direction bit set to ‘ ...
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... NXP Semiconductors 10. SPI operation SCLK SI a. Register write SCLK Register read Fig 12. SPI operation Table 13. Bit 7 6:3 2:1 0 11. Limiting values Table 14. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol tot P/out T amb T stg [1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. ...
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... NXP Semiconductors 12. Static characteristics Table 15. Static characteristics V = (2 (3.3 V 0.3 V Symbol Parameter Supplies V supply voltage DD I supply current DD Inputs I2C/SPI V HIGH-level input voltage IH V LOW-level input voltage IL I leakage current L C input capacitance i Output SO V HIGH-level output voltage OH V LOW-level output voltage ...
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... NXP Semiconductors Table 15. Static characteristics V = (2 (3.3 V 0.3 V Symbol Parameter 2 I C-bus inputs SCL, CS/A0, SI/A1 V HIGH-level input voltage IH V LOW-level input voltage IL I leakage current L C input capacitance i [1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 3.8 V steady state voltage tolerance on inputs and outputs when no supply voltage is present ...
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... NXP Semiconductors START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA Rise and fall times refer Fig 13. I C-bus timing diagram SDA GPIOn Fig 14. Write to output SLAVE ADDRESS SDA IRQ GPIOn Fig 15. GPIO pin interrupt PCA9502_3 Product data sheet bit 7 bit 6 ...
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... NXP Semiconductors Table 17. SPI-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load (2 (3.3 V 0.3 V All output load = 25 pF, unless otherwise specified. Symbol Parameter t CS HIGH to SO 3-state delay time ...
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... NXP Semiconductors CS SCLK R/W SO IRQ R A[3:0] = IOState (0x0B) Fig 18. Read IOState to clear GPIO INT PCA9502_3 Product data sheet d13 Rev. 03 — 13 October 2006 PCA9502 2 8-bit I/O expander with I C-bus/SPI interface 002aab879 © NXP B.V. 2006. All rights reserved ...
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... NXP Semiconductors 14. Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 16. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 20. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 17. Abbreviations Table 20. Acronym GPIO 2 I C-bus I/O LCD POR SPI PCA9502_3 Product data sheet ...
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... Release date PCA9502_3 20061013 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 15 “Static – supply current, operating; no load: changed maximum limit from 6 750 A for both DD 2 ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2.2 I C-bus features . . . . . . . . . . . . . . . . . . . . . . . . 1 2.3 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 7.1 Hardware reset, Power-On Reset (POR) and software reset ...