DS33X11+ Maxim Integrated Products, DS33X11+ Datasheet - Page 144

• Manufacturer Part Number: DS33X11+
• Description: IC MAPPING ETHERNET 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X11+

• Applications: Data Transport
• Interface: SPI
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 144-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

009h:
Default
Register Name:
Register Description:
Register Address:
008h:
Default
Bit 15: Microprocessor Interrupt Status (MICIS) This bit is set if the Microport has an active, enabled interrupt
condition. Normally, this condition is caused by the presence of a trapped frame for extraction and processing.
Bit 14: Decapsulation Interrupt Status 4 (DECIS4) This bit is set if Decapsulator 4 has an active, enabled
interrupt condition.
Bit 13: Decapsulation Interrupt Status 3 (DECIS3) This bit is set if Decapsulator 3 has an active, enabled
interrupt condition.
Bit 12: Decapsulation Interrupt Status 2 (DECIS2) This bit is set if Decapsulator 2 has an active, enabled
interrupt condition.
Bit 11: Encapsulation Interrupt Status 4 (ECIS4) This bit is set if Encapsulator 4 has an active, enabled interrupt
condition.
Bit 10: Encapsulation Interrupt Status 3 (ECIS3) This bit is set if Encapsulator 3 has an active, enabled interrupt
condition.
Bit 9: Encapsulation Interrupt Status 2 (ECIS2) This bit is set if Encapsulator 2 has an active, enabled interrupt
condition.
Bit 8: Receive VCAT Interrupt Status (RVCATIS) This bit is set if the receive VCAT has an active, enabled
interrupt condition.
Bit 6: Buffer Manager (Arbiter) Interrupt Status (BUFIS) This bit is set if the buffer manager has an active,
enabled interrupt condition.
Bit 4: Transmit WAN Serial Port Interrupt Status (TSPIS) This bit is set if the transmit serial WAN port has an
active, enabled interrupt condition.
Bit 3: Decapsulation Interrupt Status 1 (DECIS1) This bit is set if Decapsulator 1 has an active, enabled interrupt
condition.
Bit 2: Encapsulation Interrupt Status 1 (ECIS1) This bit is set if Encapsulator 1 has an active, enabled interrupt
condition.
Bit 1: Transmit LAN Interrupt Status (TXLANIS) This bit is set if a transmit Ethernet LAN port has an active,
enabled interrupt condition.
Bit 0: Receive LAN and Bridge Filter Interrupt Status (RXLANIS) This bit is set if either of the receive Ethernet
LAN MAC(s) or the LAN Queue Overflows have an active, enabled interrupt condition.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Bit 15
MICIS
Bit 7
0
0
-
DECIS4
BUFIS
Bit 14
Bit 6
0
0
GL.ISR
Global Interrupt Status Register
008h
DECIS3
Bit 13
Bit 5
0
0
-
DECIS2
TSPIS
Bit 12
Bit 4
0
0
DECIS1
Bit 11
ECIS4
Bit 3
0
0
ECIS3
ECIS1
Bit 10
Bit 2
0
0
TXLANIS
ECIS2
Bit 9
Bit 1
0
0
RVCATIS
RXLANIS
144 of 375
Bit 8
Bit 0
0
0