CC-W9M-NA37-XE Digi International, CC-W9M-NA37-XE Datasheet - Page 19

• Manufacturer Part Number: CC-W9M-NA37-XE
• Description: MOD WI-9M 64MB SDRAM 128MB FLASH
• Manufacturer: Digi International
• Series: -r

Specifications of CC-W9M-NA37-XE

• Module/board Type: Core Module
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Networking

Wake-up event
19
C h a p t e r 1
ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
The other power source supplies the CPU and internal logic, and should be
controlled for power on/off. In SLEEP mode, the second power supply source for the
CPU and internal logic will be turned off. The wake-up from SLEEP mode can be
issued by EINT[15:0].
In SLEEP mode, VDDi, VDDiarm, VDDMPLL and VDDEPLL will be turned off, and are
controlled by PWREN. If the PWREN signal is activated (H), VDDi and VDDiarm are
supplied by an external voltage regulator. If PWREN pin is inactive (L), VDDi and
VDDiarm are turned off.
In Power_OFF mode 1.2V have to be supplied to the VDD alive pin, and it is also
necessary to provide the I/O-voltages of 1.8V/3.3V. Therefore the LDO, which
supplies VDD alive will not be switched off.
The following describes the sequence of entering SLEEP mode:
1
2
3
4
5
6
The SLEEP mode exit sequence is as follows.
1
2
When S3C2443X wakes up from the STOP Mode by an External Interrupt, an RTC
alarm interrupt and other interrupts, the PLL is turned on automatically. The initial-
state of S3C2443X after wake-up from the SLEEP Mode is almost the same as the
Power-On-Reset state except for the contents of the external DRAM is preserved. In
contrast, S3C2443X automatically recovers the previous working state after wake-
up from the STOP Mode. The following table shows the states of PLLs and internal
clocks after wake-ups from the power-saving modes.
One of the SLEEP Mode entering events is triggered by the system software or by
the hardware.
System controller requests bus controller to finish pending transaction.
Bus controller sends acknowledgement to system controller after bus
transactions are completed.
System controller requests memory controller to enter self-refresh mode,
preserving SDRAM contents.
System controller waits for self-refresh acknowledgement from memory
controller.
After receiving the self-refresh acknowledge, disables the XTAL and PLL
oscillation and also disables the external power source for the internal logic by
asserting the PWR_EN pin to low state. The PWR_EN pin is the regulator disable
control signal for the internal logic power source.
System controller enables external power source by deasserting PWR_EN to high
state and initiates power settle down programmable through a register in the
PWRSETCNT field of RSTCON register.
System controller releases the System Reset (synchronously, relatively to the
system clock) after the power supply is stabilized.