CC-W9M-NA37-XE Digi International, CC-W9M-NA37-XE Datasheet - Page 45
CC-W9M-NA37-XE
Manufacturer Part Number
CC-W9M-NA37-XE
Description
MOD WI-9M 64MB SDRAM 128MB FLASH
Manufacturer
Digi International
Series
-r
Datasheet
1.CC-W9M-NA37-XE.pdf
(145 pages)
Specifications of CC-W9M-NA37-XE
Module/board Type
Core Module
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Networking
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High speed SPI
External
address/data bus
WLAN connectors
45
C h a p t e r 1
ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
The control lines are available on X2.
The High Speed Serial Peripheral Interface (HS_SPI) can interface the serial data
transfer. HS_SPI has two 8-bit shift registers for transmission and receiving,
respectively. During an SPI transfer, data is simultaneously transmitted (shifted out
serially) and received (shifted in serially). HS_SPI supports the protocols for National
Semiconductor Microwire and Motorola Serial Peripheral Interface.
Features:
The external address/data bus supports:
In addition to the wired Ethernet interface, the ConnectCore Wi-9M 2443 module
also offers an integrated dual-diversity 802.11a/b/g interface with data rates up to
54 Mbps. Two U.FL antenna connectors are provided on the module. For the Connect
Core Wi-9M 2443, attach the antennas with the U.FL-RP-SMA FEMALE Cable to the
CPU Interface and DMA data transfer mode
1-bit / 4-bit / 8-bit mode switch support
Auto CMD12 support
Suspend / Resume support
Read Wait operation support
Card Interrupt support
CE-ATA mode support
Full duplex support
8-bit shift register for TX/RX
8-bit prescale logic
3 clock sources
8-bit/32-bit bus interface
Motorola SPI protocol and National Semiconductor Microwire compliant
Two independent transmit and receive FIFOs (16 samples deep/32-bits wide)
Master-mode and slave-mode
Receive-without-transmit operation
64MB address space per external chip select
Programmable 8/16-bit data bus width
Four external chip selects
Complete programmable access cycles for all memory banks
External wait signals to expand the bus cycle
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