CC-W9M-NA37-XE Digi International, CC-W9M-NA37-XE Datasheet - Page 38

• Manufacturer Part Number: CC-W9M-NA37-XE
• Description: MOD WI-9M 64MB SDRAM 128MB FLASH
• Manufacturer: Digi International
• Series: -r

Specifications of CC-W9M-NA37-XE

• Module/board Type: Core Module
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Networking

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IIS block
diagram:
IIS-Bus format
The IIS bus has four lines including serial data input I2SSDI, serial data output I2SSDO,
left/right channel select clock I2SLRCLK, and serial bit clock I2SBCLK; the device
generating I2SLRCLK and I2SBCLK is the master.
Serial data is transmitted in 2's complement with the MSB first with a fixed position,
whereas the position of the LSB depends on the word length. The transmitter sends
the MSB of the next word at one clock period after the I2SLRCLK is changed. Serial
data sent by the transmitter may be synchronized with either the trailing or the
leading edge of the clock signal. However, the serial data must be latched into the
receiver on the leading edge of the serial clock signal, and so there are some
restrictions when transmitting data that is synchronized with the leading edge.
The LR channel select line indicates the channel being transmitted. I2SLRCLK may be
changed either on a trailing or leading edge of the serial clock, but it does not need
to be symmetrical. In the slave, this signal is latched on the leading edge of the clock
signal. The I2SLRCLK line changes one clock period before the MSB is transmitted.
This allows the slave transmitter to derive synchronous timing of the serial data that
will be set up for transmission. Furthermore, it enables the receiver to store the
previous word and clear the input for the next word.
MSB (Left) Justified
MSB-Justified (Left-Justified) format is similar to IIS bus format, except that in MSB-
justified format, the transmitter always sends the MSB of the next word at the same
time whenever the I2SLRCLK is changed.
LSB (Right) Justified
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