NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 111
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NS7520B-1-C36
Manufacturer Part Number
NS7520B-1-C36
Description
IC ARM MICROPROCESSOR 177BGA
Manufacturer
Digi International
Series
NET+ARM®r
Specifications of NS7520B-1-C36
Applications
Network Processor
Core Processor
ARM7
Program Memory Type
External Program Memory
Controller Series
-
Ram Size
External
Interface
EBI/EMI, Ethernet, DMA, SPI, UART
Number Of I /o
16
Voltage - Supply
1.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
177-LFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NS7520B-1-C36
Manufacturer:
Digi International
Quantity:
10 000
Part Number:
NS7520B-1-C36
Manufacturer:
NETARM
Quantity:
20 000
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Table 38: Chip Select Option Register A bit definition
WAIT[3:0]/BCYC[1:0] continued
D05:04
D03:02
Bits
R/W
R/W
Access
BSIZE
PS
Mnemonic
0
0 for
CS[4:1],
per boot-
strap for
CS0
Reset
w w w . d i g i e m b e d d e d . c o m
Burst access size in beats
00
01
10
11
Controls the maximum number of memory cycles
that can occur in a burst cycle. This field
determines only the maximum number of
allowable bus cycles; the current bus master can
choose to burst a smaller amount. If the current bus
master continues to burst, the peripheral terminates
the burst when the number of memory cycles
reaches the maximum allowed by this field.
Port size
00
01
10
11
Controls the size of the memory peripheral device:
8-, 16-, or 32-bits.
The initial state of PS for CS0 depends on
hardware initialization settings. See "NS7520
bootstrap initialization" on page 59 for more
information.
Description
When DRSEL=1 and DMODE=10
See "SDRAM," beginning on page 111.
follows the timing of a single access. CAS_
is asserted BCYC BCLK cycles for all cycles
that follow the initial cycle in a burst. If
BCYC is set to 0, the controller cannot
execute burst cycles.
The first memory cycle of a burst access
2 system bus cycles in burst access
4 system bus cycles in burst access
8 system bus cycles in burst access
16 system bus cycles in burst access
32-bit port size
16-bit port size
8-bit port size
Reserved
M e m o r y C o n t r o l l e r M o d u l e
9 9
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