NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 316
![no-image](/images/manufacturer_photos/0/1/193/digi_international_sml.jpg)
NS7520B-1-C36
Manufacturer Part Number
NS7520B-1-C36
Description
IC ARM MICROPROCESSOR 177BGA
Manufacturer
Digi International
Series
NET+ARM®r
Specifications of NS7520B-1-C36
Applications
Network Processor
Core Processor
ARM7
Program Memory Type
External Program Memory
Controller Series
-
Ram Size
External
Interface
EBI/EMI, Ethernet, DMA, SPI, UART
Number Of I /o
16
Voltage - Supply
1.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
177-LFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NS7520B-1-C36
Manufacturer:
Digi International
Quantity:
10 000
Part Number:
NS7520B-1-C36
Manufacturer:
NETARM
Quantity:
20 000
- Current page: 316 of 338
- Download datasheet (2Mb)
EDO burst errata
3 0 4
N S 7 5 2 0 e r r a t a
UART CTS Flow
Control workaround
Hardware workaround
For each UART, externally clock the CTS signal with the Txd_n signal to guarantee
that CTS will not be seen de-asserting at the start of a character.
The WAIT field in the Chip Select Option register controls the wait states of the first
cycle of an EDO burst. The wait states for the secondary cycles are controlled by the
BCYC field. Secondary cycles, therefore, are intended to be shorter than the first
cycle, for faster transfers.
When a chip select is configured as EDO, the wait states in the secondary cycles are,
incorrectly, the sum of the WAIT and BCYC fields, making the secondary cycles longer
than the first cycle.
Example
The WAIT field is set to 3 and the BCYC field is set to 1, resulting in 4 wait states in
the secondary cycles.
Note:
CTS[n]
TXD[n]
Setting the BCYC field to 0 is not an option because that produces the
maximum number of wait states:
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
63 WAIT + 15 BCYC = 78 wait states on the secondary cycles
RESET
CTS_mod[n]
Add R2 instead of U2 to bypass this circuit
U2
74LV74
Q
Q
R2
CLK
D
0 OHM
CTS[n]
TXD[n]
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