NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 150
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NS7520B-1-C36
Manufacturer Part Number
NS7520B-1-C36
Description
IC ARM MICROPROCESSOR 177BGA
Manufacturer
Digi International
Series
NET+ARM®r
Specifications of NS7520B-1-C36
Applications
Network Processor
Core Processor
ARM7
Program Memory Type
External Program Memory
Controller Series
-
Ram Size
External
Interface
EBI/EMI, Ethernet, DMA, SPI, UART
Number Of I /o
16
Voltage - Supply
1.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
177-LFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NS7520B-1-C36
Manufacturer:
Digi International
Quantity:
10 000
Part Number:
NS7520B-1-C36
Manufacturer:
NETARM
Quantity:
20 000
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D M A c h a n n e l r e g i s t e r s
Table 50: DMA Control register bit definition
D25:24
Bits
R/W
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
BTE
Mnemonic
0
Reset
Burst transfer enable
Determines whether the DMA channel can use burst
transfers through the bus. This configuration applies to
both buffer descriptor and peripheral data access.
For DMA channel 1, the BB, MODE, and BTE
configuration must be the same in all four control registers
(A, B, C, and D).
Fly-by mode:
00
01
10
11
In fly-by mode, the BTE field controls the maximum
number of operands that the DMA controller moves each
time it acquires control of the BBus.
When performing DMA to an internal peripheral, the
operand size is always 32 bits. When performing DMA to
an external peripheral, the size field determines the operand
size. The DMA controller moves information using burst
cycles. If the attached memory peripheral device cannot
support bursting or the peripheral terminates the burst, the
maximum number of bytes defined by BTE is not reached.
Memory-to-memory mode:
00
01
10
11
In memory-to-memory mode, the BTE field controls the
maximum number of bytes that the DMA controller moves
each time it acquires control of the BBus. The DMA
controller moves information using burst cycles. If the
attached source memory peripheral device cannot support
bursting or the source peripheral terminates the burst, the
maximum number of bytes defined by BTE is not reached.
Description
1 operand
2 operands
4 operands
Reserved
No burst
8-byte burst
16-byte burst
Reserved
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