NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 242

• Manufacturer Part Number: NS7520B-1-C36
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-C36

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2 3 0
S e r i a l C h a n n e l r e g i s t e r s
Table 88: Serial Channel Control Register B bit definition
D25:22
D21:20
D19
D18:16
D15
D14:12
Bit
N/A
R/W
R/W
N/A
R/W
N/A
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Reserved
MODE
BITORDR
Reserved
RTSTX
Reserved
Mnemonic
N/A
0
0
N/A
0
N/A
Reset
N/A
SCC mode
00
01
10
11
Configures the serial channel to operate in UART or
SPI modes. The MODE field must be established
before the CE bit in Serial Channel Control Register
A is set to 1.
Bit ordering
0
1
Controls the order in which bits are transmitted and
received in the Serial Shift register.
N/A
Enable active RTS only while transmitting
Note:
Controls the RTS indicator. Do not set this bit if the
RTSRX bit in Serial Channel Control Register A is
set.
When this bit is set, the RTS output goes active only
when the transmitter is actively sending a transmit
character. The RTSTX bit allows external hardware to
use the RTS signal as a transmit line driver enable
signal in
multi-drop applications.
N/A
Description
Normal; transmit/receive LSB (least significant
bit) first
Reverse; transmit/receive MSB (most significant
bit) first
processed LSB first, MSB last.
processed MSB first, LSB last.
When BITORDR is set to 0, the bits are
When BITORDR is set to 1, the bits are
UART mode
Reserved
SPI master mode
SPI slave mode
The RTS bit in Serial Channel Control
Register A must be set if setting this bit.