NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 157

• Manufacturer Part Number: NS7520B-1-C36
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-C36

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Ethernet transmitter considerations
Ethernet receiver considerations
In general, the problem of transmit underruns can be avoided by running in half
duplex rather than full duplex. Late collisions can be eliminated by proper network
design; late collisions are caused by too many cascaded levels of hubs, switches,
repeaters, and the like.
To correct an underrun condition, use these steps:
1
2
3
4
5
The transmit DMA now starts again at the beginning. The recovery is implemented in
the NET+OS BSP, no data is lost, and there is no other effect on operation.
When the DMA for an Ethernet transmit frame completes and the F bit is set in the
buffer descriptor, the packet transmission starts immediately no matter the value in
the watermark field. If the F bit is clear, packet transmission is delayed until the FIFO
contains the same number of bytes as the selected watermark. See "Ethernet General
Control register (EGCR) bit definitions" on page 158 for more information.
When an Ethernet frame is received, DMA channel 1 searches the four buffer
descriptors for the optimum buffer size. The search order is A, B, C, D. The search
stops as soon as the DMA channel finds an available buffer that is large enough to hold
the entire frame. The search also stops when the DMA channel finds a DMA Control
register whose CE bit is set to zero.
Disable the DMA channel by setting the CE bit to 0 in the DMA Control register.
Disable the transmit DMA and transmit FIFO by setting the ETXDMA and ETX bits
to 0 in the Ethernet General Control register.
Initialize the buffer descriptors and DMA buffer descriptor pointer.
Enable the transmit DMA and transmit FIFO by setting the ETXDMA and ETX bits
to 1 in the Ethernet General Control register.
Enable the DMA channel by setting the CE bit to 1 in the DMA Control register.
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