DS33ZH11+ Maxim Integrated Products, DS33ZH11+ Datasheet - Page 111

• Manufacturer Part Number: DS33ZH11+
• Description: IC MAPPER ETHERNET 100CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33ZH11+

• Applications: Data Transport
• Interface: Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 100-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 0: Receive PMU Update (RPMUU) This signal causes the receive cell/packet processor block performance
monitoring registers (counters) to be updated. A 0 to 1 transition causes the performance monitoring registers to
be updated with the latest data, and the counters reset (0 or 1). This update updates performance-monitoring
counters for the Serial Interface.
Bit 0: Receive PMU Update Status (RPMUUS) This bit is set when the Transmit PMU Update is completed. This
bit is cleared when RPMUU is set to 0.
Bit 3: SAPI High is not equal to LI.TRX86SAPIH Latched Status (SAPIHNE) This latched status bit is set if
SAPIH is not equal to LI.TRX86SAPIH. This latched status bit is cleared upon read.
Bit 2: SAPI Low is not equal to LI.TRX86SAPIL Latched Status (SAPILNE) This latched status bit is set if
SAPIL is not equal to LI.TRX86SAPIL. This latched status bit is cleared upon read.
Bit 1: Control is not equal to LI.TRX8C (CNE) This latched status bit is set if the control field is not equal to
LI.TRX8C. This latched status bit is cleared upon read.
Bit 0: Address is not equal to LI.TRX86A (ANE) This latched status bit is set if the X.86 Address field is not
equal to LI.TRX86A. This latched status bit is cleared upon read.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
-
-
7
0
7
0
-
-
LI.RHPMUU
Serial Interface Receive HDLC PMU Update Register
120h
LI.RHPMUS
Serial Interface Receive HDLC PMU Update Status Register
121h
6
-
-
6
0
6
0
-
-
LI.RX86S
Receive X.86 Latched Status Register
122h
5
-
-
5
0
5
0
-
-
111 of 172
4
-
-
0
4
0
4
-
-
SAPIHNE
3
-
3
0
3
0
-
-
SAPILNE
2
-
2
0
2
0
-
-
CNE
1
-
1
0
1
0
-
-
RPMUUS
RPMUU
ANE
0
-
0
0
0
0