DS33ZH11+ Maxim Integrated Products, DS33ZH11+ Datasheet - Page 86
![IC MAPPER ETHERNET 100CSBGA](/photos/6/94/69414/100-csbga_21-0153b_sml.jpg)
DS33ZH11+
Manufacturer Part Number
DS33ZH11+
Description
IC MAPPER ETHERNET 100CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33Z11.pdf
(172 pages)
Specifications of DS33ZH11+
Applications
Data Transport
Interface
Serial
Voltage - Supply
1.8V, 2.5V, 3.3V
Package / Case
100-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7: BERT Pattern (BSP[7:0]) Lower eight bits of 32 bits. Register description follows next register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7: BERT Pattern (BSP[15:8]) 8 bits of 32 bits. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7: BERT Pattern (BSP[23:16]) 8 bits of 32 bits. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 8: BERT Pattern (BSP[31:24]) Upper 8 bits of 32 bits. Register description below.
BERT Pattern (BSP[31:0]) These 32 bits are the programmable seed for a transmit PRBS pattern, or the
programmable pattern for a transmit or receive repetitive pattern. BSP(31) is the first bit output on the transmit
side for a 32-bit repetitive pattern or 32-bit length PRBS. BSP(31) is the first bit input on the receive side for a 32-
bit repetitive pattern.
BSP15
BSP23
BSP31
BSP7
7
0
7
0
7
0
7
0
BSP14
BSP22
BSP30
BSP6
6
0
6
0
6
0
6
0
BSPB0R
BERT Pattern Byte0 Register
84h
BSPB1R
BERT Pattern Byte 1 Register
85h
BSPB2R
BERT Pattern Byte2 Register
86h
BSPB3R
BERT Seed/Pattern Byte3 Register
87h
BSP13
BSP21
BSP29
BSP5
5
0
5
0
5
0
5
0
BSP12
BSP20
BSP28
86 of 172
BSP4
4
0
4
0
4
0
4
0
BSP11
BSP19
BSP27
BSP3
3
0
3
0
3
0
3
0
BSP10
BSP18
BSP26
BSP2
2
0
2
0
2
0
2
0
BSP17
BSP25
BSP1
BSP9
1
0
1
0
1
0
1
0
BSP16
BSP24
BSP0
BSP8
0
0
0
0
0
0
0
0
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