DS33ZH11+ Maxim Integrated Products, DS33ZH11+ Datasheet - Page 8

• Manufacturer Part Number: DS33ZH11+
• Description: IC MAPPER ETHERNET 100CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33ZH11+

• Applications: Data Transport
• Interface: Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 100-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2
2.1 General
2.2 Serial Interface
2.3 HDLC
2.4 Committed Information Rate (CIR) Controller
2.5 X.86 Support
FEATURE HIGHLIGHTS
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169-pin CSBGA package (DS33Z11)
100-pin CSBGA package for hardware/SPI modes only (DS33ZH11)
1.8V supply with 3.3V tolerant inputs and outputs
IEEE 1149.1 JTAG boundary scan
Software access to device ID and silicon revision
Development support includes evaluation kit, driver source code, and reference designs
Supports line speeds up to 52 Mbps
Supports data enable and gapped clocking
Supports byte synchronization input and output for X.86 applications
One HDLC controller engine
Compatible with polled or interrupt driven environments
Programmable FCS insertion and extraction
Programmable FCS type
Supports FCS error insertion
Programmable packet size limits (minimum 64 bytes and maximum 2016 bytes)
Supports bit stuffing/destuffing
Selectable packet scrambling/descrambling (X
Separate FCS errored packet and aborted packet counts
Programmable inter-frame fill for transmit HDLC
CIR rate controller limits transmission of data from the Ethernet interface to the serial interface
CIR granularity at 512 kbps
CIR Averaging for smoothing traffic peaks
Programmable X.86 address/control fields for transmit and receive
Programmable 2-byte protocol (SAPI) field for transmit and receive
32 bit FCS
Transmit Transparency processing—7E is replaced by 7D, 5E
Transmit Transparency processing—7D replaced by 7D, 5D
Receive rate adaptation (7D, DD) is deleted
Receive Transparency processing—7D, 5E is replaced by 7E
Receive Transparency processing—7D, 5D is replaced by 7D
Receive Abort Sequence the LAPS packet is dropped if 7D7E is detect
Self-synchronizing X
Frame indication due to bad address/control/SAPI, FCS error, abort sequence, or frame size longer
than preset max
43
+ 1 payload scrambling.
8 of 172
43
+ 1)