ISP1562BEGE ST-Ericsson Inc, ISP1562BEGE Datasheet - Page 33

IC USB PCI HOST CTRLR 100-LQFP

ISP1562BEGE

Manufacturer Part Number
ISP1562BEGE
Description
IC USB PCI HOST CTRLR 100-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1562BEGE

Applications
USB Host/Function Processor
Interface
EHCI Interface
Voltage - Supply
3 V ~ 3.6 V
Package / Case
100-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3157
ISP1562BE

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1562BEGE
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
NXP Semiconductors
11. USB Host Controller registers
Table 42.
ISP1562_2
Product data sheet
Address
0Ch
1Ch
2Ch
3Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
40h
44h
48h
USB Host Controller registers
OHCI register
HcRevision
HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcHCCA
HcPeriodCurrentED
HcControlHeadED
HcControlCurrentED
HcBulkHeadED
HcBulkCurrentED
HcDoneHead
HcFmInterval
HcFmRemaining
HcFmNumber
HcPeriodicStart
HcLSThreshold
HcRhDescriptorA
10.2 USB bus states
Reset state — When the USB bus is in the reset state, the USB system is stopped.
Operational state — When the USB bus is in the active state, the USB system is
operating normally.
Suspend state — When the USB bus is in the suspend state, the USB system is
stopped.
Resume state — When the USB bus is in the resume state, the USB system is operating
normally.
Each Host Controller contains a set of on-chip operational registers that are mapped to
uncached memory of the system addressable space. This memory space must begin on a
DWORD (32-bit) boundary. The size of the allocated space is defined by the initial value in
the Base Address register 0. HCDs must interact with these registers to implement USB
functionality.
After the PCI enumeration driver finishes the PCI device configuration, the new base
address of these memory-mapped operational registers is defined in BAR0. The HCD can
access these registers by using the address of base address value + offset.
Table 42
contains a list of Host Controller registers.
Reset value
Func0 OHCI1
0000 0010h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 2EDFh
0000 0000h
0000 0000h
0000 0000h
0000 0628h
FF00 0901h
[1]
Rev. 02 — 1 March 2007
Func1 OHCI2
0000 0010h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 2EDFh
0000 0000h
0000 0000h
0000 0000h
0000 0628h
FF00 0901h
EHCI register
CAPLENGTH/HCIVERSION
HCSPARAMS
HCCPARAMS
HCSP-PORTROUTE1[31:0]
HCSP-PORTROUTE2[59:32]
reserved
reserved
reserved
USBCMD
USBSTS
USBINTR
FRINDEX
reserved
PERIODICLISTBASE
ASYNCLISTADDR
reserved
reserved
reserved
reserved
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
ISP1562
Reset value
Func2 EHCI
0100 0020h
0000 2192h
0000 0012h
0000 0010h
0000 0000h
-
-
-
0008 0000h
0000 1000h
0000 0000h
0000 0000h
-
0000 0000h
0000 0000h
-
-
-
-
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