KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 35

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

by the DMI LMB master and the CPU become deadlocked. This situation would
then only be recoverable by a Watchdog reset.
The problem exists within the DMI DLB, which is used as a single cache line
when no data cache is configured, and as a streaming buffer when data cache
is present. As such the problem affects all load accesses to cacheable
locations, whether data cache is configured or not, since the DLB is used in both
cases.
Note: This problem affects load accesses to the on-chip Flash only. Instruction
Workaround
As described previously, this problem should not be encountered during normal
operation and will only be triggered in the case of a double-bit error being
detected in an access to the on-chip Flash.
However, in order to remove the possibility of encountering this issue, all load
accesses to cacheable addresses within the on-chip Flash should be made
using natural alignment - word transfers should be word aligned, double-word
transfers double-word aligned.
It is also possible to check for the occurrence of this problem by having some
other master, such as the PCP, periodically poll the LBCU LEATT register to
check for the occurrence of LMB error conditions, specifically if one is detected
during a BTR2 read transfer from the DMI, as reported by LEATT.OPC and
LEATT.TAG.
DMI_TC.017
OVC_OCON.DCINVAL if cache off.
A problem exists whereby the DMI line buffer is not invalidated by a write to
OVC_OCON.DCINVAL when operating with the D-cache turned off. This
means that the user cannot rely on a write to OVC_OCON.DCINVAL to make
sure that any stale data in the DMI line buffer is invalidated. This can be a
TC1797, EES-AC, ES-AC, AC
fetches which encounter a similar condition (bus error on later beat of
block transfer) behave as expected and will return a PSE trap upon any
attempt to execute an instruction from a Flash location containing a
double-bit error.
DMI line buffer
35/101
is not invalidated by a write to
Functional Deviations
Rel. 1.3, 18.12.2009
Errata Sheet