KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 38

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

EBU_TC.021 Incorrect delay calculation accessing Asynchronous mem-
ories
The EBU has the facility for the flash clock to run continuously by setting one of
the BUSRCONx.BFCMSEL to 0
same clock, then all accesses requiring a flash clock will use the
BUSRAPx.EXTCLOCK
BUSRCONx.BFCMSEL =0
various control signals enabled by the ECSE and EBSE bits.
However, no distinction was made for asynchronous regions to enable them to
use a separate method of delay calculation so, if a continuous flash clock is
enabled, signal delays for asynchronous accesses will be calculated using the
same EXTCLOCK value as that used for synchronous accesses instead of the
EXTCLOCK value in the registers of the region being accessed.
Workaround
If the continuous flash clock mode is in use, adjust the phase lengths for the
asynchronous regions to compensate for the modified signal delays.
EBU_TC.022 Write Data Delay Control for Asynchronous Memory Ac-
cesses
The EBU allows the timing of the write data driven onto the EBU_AD(31:0) pins
to
EBU_BUSWAPx.EXTCLOCK register fields. This delay mechanism is not
working as specified for asynchronous write accesses:
•
•
•
TC1797, EES-AC, ES-AC, AC
The time at which write data is disabled cannot be delayed by half a clock
cycle. Register settings where a half clock cycle delay would be expected
will result in a full clock cycle of delay.
The time at which write data is enabled is never delayed. The bus will always
be driven as if no delay was in effect. If the register settings require the data
to be delayed then invalid data will be driven for the delay period.
The time at which valid write data is driven cannot be delayed by half a clock
cycle. Register settings where a half clock cycle delay would be expected
will result in no delay being applied.
be
adjusted
using
setting
B
when determining the correct delays for the
B
. In this case, as all attached devices see the
38/101
the
from
EBU_BUSWCONx.ECSE
the
region
Functional Deviations
Rel. 1.3, 18.12.2009
which
Errata Sheet
and
has