KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 72

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

OCDS_TC.025 PC corruption when entering Halt mode after a MTCR to
DBGSR
In cases where the CPU is forced into HALT mode by a MTCR instruction to the
DBGSR register, there is a possibility of PC corruption just before HALT mode
is entered. This can happen for MTCR instructions injected via the CPS as well
as for user program MTCR instructions being fetched by the CPU. In both cases
the PC is potentially corrupted before entering HALT mode. Any subsequent
read of the PC during HALT will yield an erroneous value. Moreover, on exiting
HALT mode the CPU will resume execution from an erroneous location. .
The corruption occurs when the MTCR instruction is immediately followed by a
mis-predicted LS branch or loop instruction. The forcing of the CPU into HALT
takes priority over the branch resolution and the PC will erroneously be
assigned the mispredicted target address before going into HALT.
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Workaround
External agents should halt the CPU using the BRKIN pin instead of using CPS
injected writes to the CSFR register. Alternatively, the CPU can always be
halted by using the debug breakpoints. Any user software write to the DBGSR
CSFR should be followed by a dsync.
OCDS_TC.026 PSW.PRS updated too late after a RFM instruction.
When a breakpoint with an associated TRAP action occurs, the Tricore will
enter a special trap called a ’debug monitor’. The RFM instruction (return from
TC1797, EES-AC, ES-AC, AC
Problem sequence 1:
1) CPS-injected MTCR instruction to DBGSR sets HALT Mode
2) LS-based branch/loop instruction
3) LS-based branch/loop is mispredicted but resolution is overridden by
HALT.
Problem sequence 2:
1) User code MTCR instruction to DBGSR sets HALT Mode
2) LS-based branch/loop instruction
3) LS-based branch/loop is mispredicted but resolution is overridden by
HALT.
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Functional Deviations
Rel. 1.3, 18.12.2009
Errata Sheet