WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 134

• Manufacturer Part Number: WG82577LM S LGWR
• Manufacturer: Intel

Specifications of WG82577LM S LGWR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Note:
10.2.1.1.6
127
For an MDI Write cycle the sequence of events is as follows:
An MDI read or write might take as long as 64 ms from the CPU write to the Ready bit
assertion.
If an invalid opcode is written by software, the MAC does not execute any accesses to
the 82577 registers.
If the 82577 does not generate a zero as the second bit of the turnaround cycle for
reads, the MAC aborts the access, sets the E (error) bit, writes 0xFFFF to the data field
to indicate an error condition, and sets the ready bit.
Future Extended NVM Register - FEXTNVM (0x00028; RW)
This register is initialized to a hardware default only at LAN_RST# reset. Software
should not modify these fields to values other than their recommended values. Bits
15:0 of this register are loaded from the NVM word 0s19 and bits 31:16 are loaded
from the NVM word 0x1A.
0
1
2
3
4
5
6
7. The CPU might read the data from the MII register and issue a new MDI command.
1. The CPU performs a write cycle to the MII register with:
2. The MAC applies the following sequence on the MDIO signal to the 82577:
3. The MAC asserts an Interrupt indicating MDI done if the Interrupt Enable bit was
4. The MAC sets the Ready bit in the MII register to indicate step 2 has been
5. The CPU might issue a new MDI command.
Bits
set.
completed.
— Ready = 0b
— Interrupt Enable bit set to 1b or 0b
— Op-Code = 01b (write)
— PHYADD = The 82577 address from the MDI register
— REGADD = The register address of the specific register to be accessed (0
— Data = specific data for desired control of the 82577
— <PREAMBLE><01><01><PHYADD><REGADD><10><DATA><IDLE>
through 31)
RW/SN
RW/SN
RW/SN
RW/SN
RW/SN
RW/SN
RW/SN
Type
82577 GbE PHY—Intel
0b
0b
0b
0b
0b
0b
0b
Reset
Reserved
dma_clk_enable_d. Enable dynamic clock stop. When this bit is set to 1b,
clk is always ticking. The default value is 0b (hardware and NVM).
wake_dma_clk_enable_d. Enable dynamic clock stop. When this bit is set
to 1b, clk is always ticking. The default value is 0b (hardware and NVM)
gpt_clk_enable_d. Enable dynamic clock stop. When this bit is set to 1b,
clk is always ticking. The default value is 0b (hardware and NVM)
mac_clk_enable_d. Enable dynamic clock stop. When this bit is set to 1b,
clk is always ticking. The default value is 0b (hardware and NVM)
m2k_clk_enable_d. Enable dynamic clock stop. When this bit is set to 1b,
clk is always ticking. The default value is 0b (hardware and NVM).
Invalid Image CSUM. When cleared, this bit indicates to the Intel NVM
programming tools that the image CSUM needs to be corrected. When set
the CSUM is assumed to be correct.
®
5 Series Express Chipset MAC Programming Interface
Description