WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 90
WG82577LM S LGWR
Manufacturer Part Number
WG82577LM S LGWR
Description
Manufacturer
Intel
Datasheet
1.WG82577LM_S_LGWR.pdf
(195 pages)
Specifications of WG82577LM S LGWR
Lead Free Status / Rohs Status
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8.10.2
Table 66.
83
Host Wake Up Control Status Register Description
Receive Control – RCTL PHY Address 01, Page 800, Register 0
RW
RW
RW
RW
RW
RW
RW
RW
RW
2. Address setting; The software device driver performs a write cycle to the MDI
3. Writing a register; the software device driver performs a write cycle to the MDI
Attribute
register with:
a. Ready = 0b
b. Op-Code = 01b (write)
c.
d. REGADD = 0x11 (address set)
e. DATA = XXXX (address of the register to be read)
register with:
a. Ready = 0b
b. Op-Code = 01b (write)
c.
d. REGADD = 0x12 (data cycle for write)
e. DATA = YYYY (data to be written to the register)
PHYADD = The 82577’s address from the MDI register
PHYADD = The 82577’s address from the MDI register
0
1
2
4:3
5
6
7
8
15:9
Bit(s)
0b
0b
1b
00b
0b
0b
0b
0b
0x00
Initial
Value
Unicast Promiscuous Enable (UPE)
0b = Disabled.
1b = Enabled.
Multicast Promiscuous Enable (MPE)
0b = Disabled.
1b = Enabled.
Slave Access Enable
0b = Access disabled, the filters are active.
1b = Access enabled, the filters are not active.
Multicast Offset (MO)
This determines which bits of the incoming multicast address are used in
looking up the bit vector.
00b = [47:38].
01b = [46:37].
10b = [45:36].
11b = [43:34].
Broadcast Accept Mode (BAM)
0b = Ignore broadcast (unless it matches through exact or imperfect filters)
1b = Accept broadcast packets.
Pass MAC Control Frames (PMCF).
0b = Do not (specially) pass MAC control frames.
1b = Pass any MAC control frame (type field value of 0x8808).
Receive Flow Control Enable (RFCE)
Indicates that the 82577 responds to the reception of flow control packets. If
auto-negotiation is enabled, this bit is set to the negotiated duplex value.
Reserved
Reserved
82577 GbE PHY—Programmer’s Visible State
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